Reversible circuit design for GCD computation in cryptography algorithms

We propose a novel algorithm for integer’s greatest common divisor (GCD) computation that hybridises both Euclidian and binary algorithms according to a new schema, in order to accelerate the GCD computation especially in the case of large bit difference between the two inputs. The proposed algorithm run slightly faster than existing algorithms and is very much easier to implement. We provide a simple proof of correctness for the algorithm, and we show that best performances can be achieved for large integers when subtraction operator complexity is relatively low with respect to the division one.

We propose an algorithm to compute a greatest common divisor (GCD) of univariate polynomials with large integer coefficients on Graphics Processing Units (GPUs). At the highest level, our algorithm relies on modular techniques to decompose the problem into subproblems that can be solved separately. Next, we employ resultant-based or matrix algebra methods to compute a GCD of each modular image in parallel. Our approach exhibits block structure to distribute the computation of a single modular GCD over several thread blocks, and thus to remove any hardware limitations on the maximal size of polynomials that can be handled. To "combine" all modular results, we have adopted Mixed-Radix Conversion (MRC) algorithm running on the GPU. Our approach shows a significant speed-up over host-based GCD algorithm from Maple 13.

In this paper, a two-dimensional (2D) Hankel theory is developed. It is shown that the degree of a 2D transfer function is determinable from the rank of its Hankel matrix. The developed theorem encompasses the one-dimensional Hankel matrix as a special case. The result is useful in the computation of the greatest common divisor. It may also be useful in identification, realization, partial realization and coding problems.

In the first part of this paper, we present an algorithm that computes an unmixed-dimensional decomposition of a varietyV. EachVi in the decompositionV=V1U...UVm is given by a finite set of polynomials which represents the generic points of the irreducible components ofVi. The basic operation in our algorithm is the computation of greatest common divisors of univariate polynomials over extension fields given by regular chains. No factorization is needed. In the second part, this algorithm is applied to geometry theorem proving. We show that it can be used for deciding whether geometry statements are generically true or whether they are true under given nondegeneracy conditions. If a geometry statement is generically true, the simplest nondegeneracy condition with respect to a lexicographical degree ordering can be constructed by means of our algorithm.

A discussion is presented of parallel division algorithms that can be classified among modified higher radix nonrestoring online division methods, where redundant representations are extensively utilized to speed up the operation. The network realizations of these algorithms are cellular, or even systolic with exclusively local control; they have both size (area) and time of O(n), where n is the length of the dividend representation. The same structures can also be used as a signed, digit-serial multiplier. When suitably equipped with some control and a few registers, the divider/multiplier brings remarkable performance to large modular arithmetic, RSA cryptography, and greatest common divisor computations. They are also of interest for the design of floating-point units and signal processing applications.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The Advanced Encryption Standard (AES), also known as a specification for the encryption of electronic data. AES is comparatively highly secure and more efficient than well-known other cryptographic algorithms and existing Data Encryption Standard (DES). This work is focused in analyzing selecting valuable research publications on AES. This also discusses some machine learning techniques such as artificial neural network (ANN) used to protect side channel attack for images. Besides this, many other recent developments such as effective differential power analysis (DPA) technique and hybrid encryption algorithm using LZW have been discussed and analyzed in details. Finally, the paper concludes with a systematic analysis of different types of attacks on AES and some future research aspects in this context. Finally, this work also proposes a new model for attack detection in AES.

In the midst of emerging technology, reversible computing is promising due to its application in the field of quantum computing. The computing hardware plays a significant role in digital signal processing DSP and multimedia application; one such major computing hardware is multiplier. It is a practice to choose multiplier to compute square of an operand. Multiplication hardware requires more elementary computations which leads to performance degradation in terms of reversible performance metrics like quantum cost, garbage outputs, and ancilla inputs. Ancilla inputs and garbage outputs are overhead bits in a reversible circuit. Reversible quantum computers of many qubits are extremely difficult to realize, thus we propose garbageless circuit design for reversible square computation. The proposed design methodology is based on recursion. Recursion technique is adapted from Karatsuba's recursive method to compute square of an operand; we designed inverse computation units to retrieve the inputs and obtain garbageless circuit. On comparing proposed circuit design with existing reversible square designs and Karatsuba multiplier design, we observed that our work improves number of input lines which includes data lines and ancilla lines.

Encryption chips are specialized integrated circuits that incorporate encryption algorithms for data encryption and decryption, ensuring data confidentiality and security. In China, the domestic SM4 algorithm is commonly utilized, as opposed to the international AES encryption algorithm. These widely implemented encryption standards have been proven to be difficult to crack through crypt analysis methods Currently, power consumption side-channel attacks are the most prevalent method. They involve capturing power consumption data during the encryption process and subsequently recovering the encryption key from this data. The two leading methods are Differential Power Analysis (DPA) and machine learning techniques. DPA does not necessitate prior knowledge but relies heavily on the number of power consumption curves. With only 50 power consumption data points, the accuracy is a mere 80%. Machine learning methods require prior knowledge, achieving an accuracy rate above 95% with only 30 power traces, albeit with training times typically exceeding 15 min. In this paper, a distributed energy analysis attack approach was presented based on Correlation Power Analysis (CPA). The power consumption data was divided into 16 subsets, with each subset corresponding to 8 bytes of the key. By training each subset separately, the 8-byte key’s corresponding power consumption data is reduced to only 100 dimensions, resulting in a 76% decrease in cracking time and a 3% improvement in cracking accuracy rate.This article also trains a more complex 256 classification model to directly crack the final key, achieving a success rate of 28% in cracking 128-bit passwords with only 1 power trace

The FDFM (Few DSP slices and Few block Memories) approach is an efficient approach which implements a processor core executing a particular algorithm using few DSP slices and few block RAMs in a single FPGA. Since a processor core based on the FDFM approach uses few hardware resources, hundreds of processor cores working in parallel can be implemented in an FPGA. The main contribution of this paper is to develop a processor core that executes Euclidean algorithm computing the GCD (Greatest Common Divisor) of two large numbers in an FPGA. This processor core that we call GCD processor core uses only one DSP slice and one block RAM, and 1280 GCD processors can be implemented in a Xilinx Virtex-7 family FPGA XC7VX485T-2. The experimental results show that the performance of this FPGA implementation using 1280 GCD processor cores is 0.0904μs per one GCD computation for two 1024-bit integers. Quite surprisingly, it is 3.8 times faster than the best GPU implementation and 316 times faster than a sequential implementation on the Intel Xeon CPU.

In order to protect a cryptographic algorithm against Power Analysis attacks, a well-known method consists in hiding all the internal data with randomly chosen masks.Following this idea, an AES implementation can be protected against Differential Power Analysis (DPA) by the “Transformed Masking Method”, proposed by Akkar and Giraud at CHES’2001, requiring two distinct masks. At CHES’2002, Trichina, De Seta and Germani suggested the use of a single mask to improve the performances of the protected implementation. We show here that their countermeasure can still be defeated by usual first-order DPA techniques.In another direction, Akkar and Goubin introduced at FSE’2003 a new countermeasure for protecting secret-key cryptographic algorithms against high-order differential power analysis (HO-DPA). As particular case, the “Unique Masking Method” is particularly well suited to the protection of DES implementations. However, we prove in this paper that this method is not sufficient, by exhibiting a (first-order) enhanced differential power analysis attack. We also show how to avoid this new attack.KeywordsTamper-resistant devicesSide-Channel attacksPower AnalysisDPATransformed Masking MethodUnique Masking MethodDESAES

Reversible logic is widely used in optical information processing, bioinformatics and quantum computing etc. Reversible logic requires ancilla inputs and garbage outputs to keep reversibility. However, it needs to reduce the number of these logic bits in complex designs, such as reversible quantum multipliers. In the existing literatures, researchers have optimized the multi-operand addition part and the partial product generation part of reversible quantum multipliers separately, which produce considerable overhead in terms of garbage outputs and ancilla inputs. This paper presents a novel method to reduce garbage outputs and ancilla inputs of reversible quantum multipliers. The proposed methodology converts some garbage outputs of the previous calculation to zeros, which are then served as ancilla inputs of the later calculation. In order to verify the proposed method, we apply it to two typical reversible quantum multiplier designs. Results show that the proposed method can greatly reduce the number of garbage outputs and ancilla inputs compared to the existing designs.

Side channel analysis(SCA) focuses on attacking cryptographic algorithm implementations by collecting leaked information and analyzing the correlation between the leaked and key information in the cryptographic system. Currently, SCA is the main threat to cryptographic implementations, with DPA (differential power analysis) and DFA (differential fault analysis) being two of the most threatening types of SCA. However, the existing countermeasures against DPA and DFA have shortcomings and can hardly protect cipher designs perfectly. Based on a comprehensive analysis of DPA and DFA, this paper proposes a new idea of using an evolutionary cipher (EVOC) against DPAs based on the model proposed by Kocher, and several different new types of DFAs. In fact, an EVOC is a kind of dynamic cipher designing method. Moreover, combined with intelligent searching algorithms and cryptography design policies, EVOCs utilize the dynamic and unpredictable properties of TRNG (a truly random number generator) to ensure cipher design at a high level of security. Therefore, with an EVOC we could design cryptography algorithms with high security to resist mathematical analysis as well as DPAs and DFAs. This paper analyzes and proves the security, efficiency, cost, and original features of EVOCs against DPA and DFA both theoretically and experimentally. Compared with existing countermeasures against SCAs, EVOCs use dynamic non-linear operations to destroy the bases of DPA and DFA. At the algorithm level, EVOCs are more efficient than other resistance methods. Based on the theory and experiments, this paper proposes certain modifications to the EVOC in the AES (advanced encryption standard) algorithm, which can be referenced by other dynamic designs of cryptographic algorithms.

Arithmetic Logic Unit (ALU) as one of the main parts of any computing hardware plays an important role in digital computers. In quantum computers which can be realized by reversible logics and circuits, reversible ALUs should be designed. In this paper, we proposed three different designs for reversible 1-bit ALUs using our proposed 3×3 and 4×4 reversible gates called MEB3 and MEB4 (Moallem Ehsanpour Bolhasani) gates, respectively. The first proposed reversible ALU consists of six logical operations. The second proposed ALU consists of eight operations, two arithmetic, and six logical operations. And finally, the third proposed ALU consists of sixteen operations, four arithmetic operations, and twelve logical operations. Our proposed ALUs can be used to construct efficient quantum computers in nanotechnology, because the proposed designs are better than the existing designs in terms of quantum cost, constant input, reversible gates used, hardware complexity, and functions generated.

Cryptographic systems can potentially suffer from various attacks which are a consequence of vulnearability of side channel information to analysis attacks. The nature of digital circuits is prone to electromagnetic and power analysis (EMA and PA) attacks. Interconnects in cryptographic circuits emanate information through electromagnetic signals which can be exploited using EMA. Complementary Metal Oxide Semiconductor (CMOS) circuits are vulnearable to leak of computational information through leakage and dynamic power consumption. Dynamic power consumption of cryptographic engines is a rich source to sink in the data under process. The hardware implementation of cryptographic algorithms undermine the security of encrypted system against non brute-force-attacks. The attackers collect and analyse the leakage information of cryptographic circuits to detect the secrete key. The parameters sensitivity of the device and circuits make the cryptographic engines vulnearable to fault injection and inherent inconsistency of the circuits. Dynamic and static power comprise two major components of power consumption of digital circuits. Both power components vary with data under process. This exhibits power consumption has data dependency in digital circuits. To make noisy power profile, various countermeasures have been proposed against Differential Power Analysis (DPA) attacks. In this research, false glitch cells is proposed to work as a countermeasure to generate random transitions and power spikes to scramble power profile. The mathematical foundation of security implications of false glitch cells against Correlation Power Analysis (CPA) attacks is investigated. Moreoever, the security efficiency of utilizing false glitch cells is verified with different metrics.

Reversible logic preserves information and provides low power computing. Floating point multiplier is an important part of arithmetic in DSP applications. IEEE754 provide two basic and widely used formats for representing floating point numbers namely Single Precision Floating point (SPFP) and Double Precision Floating Point (DPFP). In this paper, we have proposed designs for Reversible SPFP and DPFP point multiplier which requires optimum design of 24X24 and 53X53 multiplying circuitry with reversible gates respectively. Also we presented sign bit calculation and exponent bit calculation circuits by reversible logic. Reversible Mantissa bits calculation circuitry requires consumes more area as it has large value of quantum cost and garbage outputs as compare to reversible sign bit and exponent bits calculation circuitry. So, we mainly focused our work on to minimize the area consumed by the reversible mantissa bits calculation circuit by minimizing the value of quantum cost and garbage outputs of it. In this paper, we presented two ways for partial products generation with reversible gates. We propose a new design of reversible 12X12 reversible Wallace tree multiplier for single precision and double precision mantissa multiplier circuit. Also 5X5 and 5X12 reversible Wallace tree multiplier for double precision multiplier. Here we use the optimized designs of reversible half adder, Full adder and 4:2 compressors. In the final summation stage, we carefully shifted the product terms and add them. For this stage we have carefully chosen the adders and compressor in such way to get the optimized results in terms of quantum cost and Garbage output. We have also shown the improvement in single precision floating point multiplier in terms of Quantum cost and Garbage output.