Scanning capacitance microscopy measurements using diamond-coated probes

Quantitative dopant profile measurements are performed on a nanometer scale by scanning capacitance microscopy (SCM). An atomic force microscope is used to position a nanometer scale tip at a semiconductor surface, and local capacitance change is measured as a function of sample bias. A new feedback method has been demonstrated in which the magnitude of the ac bias voltage applied to the sample is adjusted to maintain a constant capacitance change as the tip is scanned across the sample surface. A quasi-1D model is used to extract dopant density profiles from the SCM measurements. The inverted SCM dopant profiles are compared with profiles obtained by process simulation and secondary ion mass spectroscopy measurement. Good agreement was found between the SCM measured profile and the lateral profile predicted by SUPREM 4 over the concentration range from 1017 to 1020 cm−3.

Improved reproducibility in scanning capacitance microscopy for quantitative 2D carrier profiling on silicon

Scanning capacitance microscopy (SCM) is a powerful tool for two-dimensional (2D) dopant/carrier profiling. Currently noise limits the accuracy of 2D dopant profiles obtained by SCM. In an effort to reduce noise, a systematic analysis of different SCM noise sources is provided. The main noise sources during SCM measurements are capacitance sensor noise and oxide–semiconductor surface induced noise. For adequate tip size, the dominant noise in SCM measurements is caused by variations in the quality of surface. On as-polished surfaces, nonstationary noise is observed. This noise is likely caused by the variations in the density of oxide traps. Tip induced charging of these traps and local variations or fluctuations in discharge time during SCM imaging cause the noise level and noise pattern to be different from image to image. Heat treatment under ultraviolet irradiation or in a hydrogen ambient is found to be an effective way to reduce or even eliminate this type of SCM noise. Stationary surface noise is mostly created by the variations in the oxide thickness. This type of noise correlates with topographic roughness and is very consistent during SCM measurements. By reducing the topographic roughness, the stationary surface noise may be reduced to the level of ∼10−2 of the depletion SCM signal for typical experimental conditions. It is shown that the capacitance sensor noise depends on the capacitance sensor tuning parameters and under proper conditions can be reduced to a negligible level for standard probe tips used in SCM measurements.

Scanning capacitance microscopy (SCM) using a dV/dC signal has been proposed for local mapping of interface traps in an insulator/semiconductor structure. In conventional SCM measurements using a dC/dV signal, it is difficult to accurately analyze the spatial distribution of interface traps from the obtained SCM images because the dC/dV signal is inversely proportional to the interface trap density. In the proposed technique, however, the spatial distribution of the interface traps can be characterized using the dV/dC signal, which is directly proportional to the interface trap density. The effectiveness of the proposed technique has been demonstrated by characterizing the spatial distributions of the interface traps in HfSiO/Si structures before and after H2 annealing. The dV/dC images obtained reveal that the spatial variation in the interface trap density is reduced by H2 annealing. Consequently, SCM measurements using a dV/dC signal have been verified to effectively characterize the spatial distribution of interface traps.

The SiO2/Si interfaces of the 2 nm thick dry oxide using rapid thermal oxidation and wet oxide using H2O formed by catalysis of Pt were investigated in order to understand the difference between the two oxides relevant to the device reliability using various methods. The interstitial defects at the interfacial region were detected using medium energy of ion scattering spectroscopy in the sample of dry oxidation, but not in the wet oxidation. The interfacial roughness and the interstitial defects strongly depended on the oxidation process, although the interfacial strain differs very little between the dry and wet oxidation processes. The results of high resolution x-ray photoelectron spectroscopy using a synchrotron radiation source clearly provided the difference of the defects between two oxides. The scanning tunneling microscope image of the SiO2 layers subjected to hot electron injection from the tip showed that wet oxide had superior quasi-breakdown characteristics to dry oxide. Time-dependent dielectric breakdown of the SiO2 layer also depended on the oxidation process, indicating that the interface roughness and the defects critically affect the reliability of the gate oxide. Thus the wet oxidized SiO2 film is found to be more stable against the dielectric breakdown than the dry oxidized sample.

The surface morphology and the electrical activation of P+ implanted 4H-SiC were investigated with respect to annealing treatments that differ only for the heating rate. P+ implantation was carried out in lightly doped n-type epitaxial layers. The implantation temperature was 300 °C. The computed P profile was 250 nm thick with a concentration of 1×1020 cm-3. Two samples underwent annealing at 1400 °C in argon with different constant ramp up rates equal to 0.05° C/s and 40 °C/s. A third sample underwent an incoherent light Rapid Thermal Annealing (RTA) at 1100 °C in argon before the annealing at 1400 °C with the lower ramp rate. The ramp up of the RTA process is a few hundred degrees per second. Atomic Force Microscopy (AFM) micrographs pointed out that the surface roughness of the samples annealed at 1400 °C increases with increasing heating rate and that the critical temperature for surface roughening is above 1100 °C. Independently on the annealing cycle, Scanning Capacitance Microscopy (SCM) measurements showed that the P profiles are uniform over the implantation thickness and have plateau concentration around 9×1018 cm-3 in all the implanted samples. The fraction of P atoms activated as donors is 13% of the total implanted fluence.

Radiation effects on wet- and dry-oxide metal-oxide-semiconductor devices

Isothermal oxidation of TiC was studied using powder sample at 300–400°C in Ar/O2 = 95/5 kPa (dry oxidation) and Ar/O2/H2O = 90/5/5–10 kPa (wet oxidation), and at 520–650°C in Ar/H2O = 95/5–15 kPa (H2O oxidation) by monitoring weight changes. The phases produced were identified by X-ray analysis and the oxidized sample was observed by scanning and transmission electron microscopy. The dry, wet and H2O oxidation of TiC was found to be described by a one-dimensional diffusion-controlling equation. It was revealed that the oxidation was divided into three steps, slow step I, fast step II, and slow step III. Water vapor in the wet oxidation accelerated these three steps, particularly step II. Non-isothermal oxidation of TiC was also performed to simultaneously monitor the evolved gases (CO/CO2, H2, CH4) with weight changes by thermogravimetry and mass analysis. The accelerating effect of water vapor on oxidation of TiC was discussed from kinetic and thermoanalytical viewpoints.

In this paper we investigate the dopant quantification error introduced in scanning capacitance microscopy measurements by the nonlinearity of the capacitance-to-voltage characteristic of MOS structures. The C-V response of the measurement set up is derived by finite element simulation and the systematic error introduced by signal processing is quantified by harmonic distortion analysis. It is shown that the investigated effect can lead to a systematic overestimate of the dopant concentration ranging from a factor of 2 up to a factor of 20, depending on the experimental conditions.

Wet and dry oxide films-4H-SiC epitaxial (0001¯) C-face interfaces have been characterized by capacitance-voltage (C-V) measurements and soft x-ray excited photoemission spectroscopy (SX-PES) and hard x-ray excited photoemission spectroscopy (HX-PES) using synchrotron radiation. The interface state density for wet oxidation is much smaller than that for dry oxidation at any energy level. In the PES measurements, intermediate oxidation states such as Si1+ and Si3+ were observed. In addition, the areal densities of these states were found to be in a good correspondence with those of the interface states. The reasons for the good electrical characteristics of metal-oxide-semiconductor devices fabricated by wet oxidation are discussed in terms of the depth profiles of oxide films derived from the SX-PES and HX-PES results.

The interface between silicon (100) and thermal silicon dioxide grown by wet, dry, and trichloroethylene oxidation has been investigated by scanning tunneling microscopy and scanning tunneling spectroscopy. The scanning tunneling microscopy images of the silicon surface, after removal of oxide, reveal the presence of silicon bumps (protrusions) in samples prepared by wet and dry oxidation while no protrusions are seen at the interface of trichloroethylene oxidized samples. The spectroscopic measurements predict that these are silicon protrusions and are produced by oxide growth conditions. X-ray photon spectroscopy on samples containing protrusions also supports the above prediction. Thus, our study suggests that roughness of the silicon–silicon dioxide interface depends on oxide growth conditions and a relatively smooth interface is obtained by tricholoroethylene oxidation.

Optical and electrical characterizations of 4H-SiC–oxide interfaces by spectroscopic ellipsometry and capacitance–voltage measurements

The speed limitations conventionally encountered in scanning tunneling microscopy, scanning capacitance microscopy, and atomic force microscopy result from the external electronics and are not inherent to the techniques themselves. Ultrafast time resolution faster than the bandwidth of the measuring electronics can be achieved by combining these techniques with picosecond optical excitation and utilizing inherent nonlinearities in the physical system. We demonstrate this idea by directly measuring carrier relaxation times at the Si(111)-(7×7) surface on the nanosecond time scale via scanning capacitance microscopy measurements of the surface photovoltage.

TMAH etching of silicon and the interaction of etching parameters

This paper reports the results of experiments designed to optimize the total dose ionizing radiation hardness of CMOS/SOS devices. Type 4007 inverter circuits were fabricated with variations in the process, including wet versus dry gate oxidation. Tolerable values (e. g. < l#x003BC;A per mil of channel width) of post-radiation n-channel back leakage were obtained only with wet oxides. Threshold shifts of ≤1V for the n-channel devices and ≤2V for the p-channel devices were obtained after 106 rads (Si) on the best devices fabricated.