Noise in scanning capacitance microscopy measurements

Scanning capacitance microscope (SCM) images, and the two-dimensional (2D) dopant profiles extracted from them, show poor reproducibility from laboratory to laboratory. Major factors contributing to SCM image variability include: poor sample surface and oxide quality, excess carrier generation from stray light, reduced sensor dynamic range from stray capacitance, and use of nonoptimal SCM operating voltages. This article discusses the sources of SCM image variability, how they affect the measured SCM images, and possible approaches for mitigating their effects. Recommended procedures for extracting quantitative 2D are discussed. Finally, a set of informal research materials is introduced consisting of a complementary metal-oxide-semiconductor transistor pair, an identical pair without metallization, and a pair of transistor-like structures with the conductivity type of the source/drains reversed. These structures are intended for use with the FASTC2D software to help improve laboratory-to-laboratory dopant profile reproducibility.

Scanning capacitance microscopy (SCM) using a dV/dC signal has been proposed for local mapping of interface traps in an insulator/semiconductor structure. In conventional SCM measurements using a dC/dV signal, it is difficult to accurately analyze the spatial distribution of interface traps from the obtained SCM images because the dC/dV signal is inversely proportional to the interface trap density. In the proposed technique, however, the spatial distribution of the interface traps can be characterized using the dV/dC signal, which is directly proportional to the interface trap density. The effectiveness of the proposed technique has been demonstrated by characterizing the spatial distributions of the interface traps in HfSiO/Si structures before and after H2 annealing. The dV/dC images obtained reveal that the spatial variation in the interface trap density is reduced by H2 annealing. Consequently, SCM measurements using a dV/dC signal have been verified to effectively characterize the spatial distribution of interface traps.

We report scanning capacitance microscopy (SCM) images of a working p-channel metal–oxide–semiconductor field-effect transistor (P-MOSFET) during device operation. Independent bias voltages were applied to the source/gate/drain/well regions of the MOSFET during SCM imaging, and the effect of these voltages on the SCM images is discussed.

In order to demonstrate its unique capabilities, a combined microscope comprised of a scanning capacitance microscope and a contact mode atomic force microscope was used to image a buried structure. The atomic force microscopy images surface topography, while the scanning capacitance microscope simultaneously images buried structure. By applying a modulation technique, the voltage derivative of the capacitance (dC/dV) was used as a scanning capacitance microscope signal. The sample used for the demonstration was a silicon wafer with metal lines 4 nm in thickness covered by a 40-nm-thick layer of silicon oxide. The scanning capacitance microscope image was dependent on the bias voltage applied to the probe and the sample. Since the scanning capacitance microscope signal above the metal lines is zero, the bias voltage dependency of the contrast in scanning capacitance microscope images corresponds directly to the scanning capacitance microscope signal versus V at locations where the metal line is not buried. However, the bias dependency of the contrast did not agree with the scanning capacitance microscope signal observed between metal lines. A possible mechanism for the discrepancy between these bias dependencies is discussed based upon charge deposition on the sample surface caused by tip contact and lateral movement of the charges in the adsorbed water on the sample surface.

Scanning capacitance microscopy (SCM) has been applied to microscopic characterization of electrical properties of silicon-on-insulator (SOI) wafers. Two kinds of capacitance-voltage (C-V) methods have been proposed for separately characterizing the electrical properties of a gate oxide, an SOI layer, a buried oxide (BOX) layer. a Si substrate, and their interfaces: (i) a front-gate C-V method whereby the electrical properties of the gate oxide and front SOI (the gate oxide/SOI) interface can be characterized. arid (ii) a back-gate C-V method for the characterization of the electrical properties of the BOX layer. back SOI (the BOX/SOI) interface, and the BOX/Si substrate interface. Furthermore, SCM images of the sampled SOI wafer have been obtained for visualizing the microscopic spatial distribution of electrical properties of SOI wafers by using the proposed C-V methods. These SCM images revealed the fluctuation in tile oxide charges arid interface traps. SCM has been demonstrated to be an effective tool for microscopic electrical characterization of SOI wafers.

Quantitative dopant profile measurements are performed on a nanometer scale by scanning capacitance microscopy (SCM). An atomic force microscope is used to position a nanometer scale tip at a semiconductor surface, and local capacitance change is measured as a function of sample bias. A new feedback method has been demonstrated in which the magnitude of the ac bias voltage applied to the sample is adjusted to maintain a constant capacitance change as the tip is scanned across the sample surface. A quasi-1D model is used to extract dopant density profiles from the SCM measurements. The inverted SCM dopant profiles are compared with profiles obtained by process simulation and secondary ion mass spectroscopy measurement. Good agreement was found between the SCM measured profile and the lateral profile predicted by SUPREM 4 over the concentration range from 1017 to 1020 cm−3.

Diamond-coated cantilevers have been used for scanning capacitance microscopy (SCM) as an alternative for metal-coated cantilevers in order to improve the stability of probes. It is shown that the diamond-coated probes produce adequate intensity of dC signal and high contrast for both p-type and n-type silicon samples and also provide superior endurance characteristics to metal-coated probes. Due to the robustness of the diamond-coated probes, we are able to evaluate the reproducibility of measurements and the homogeneity of the ultrathin oxide for both dry oxidation (heated up to 300 °C in air under ultraviolet illumination) and wet oxidation (immersed into a hydrogen peroxide solution at 70 °C). The dry oxidation shows better reproducibility, while the wet oxidation shows better homogeneity. Finally, comparison of SCM with secondary ion mass spectrometry measurement shows that diamond-coated probes can be used at least for one-dimensional quantitative SCM measurements without any significant effect of depletion in the diamond-coated tip itself.

Scanning capacitance microscopy (SCM) is currently one of the most promising tools for twodimensional carrier profiling. This technique, based upon atomic force microscope (AFM) operated in the contact mode, uses a conductive probe which is scanned over the semiconductor surface. The conductive probe, oxide on the surface of the semiconductor, and the semiconductor substrate form a metal-oxide-semiconductor (MOS) structure. An a.c. bias is applied to the tip and the capacitance of the MOS structure is monitored. The a.c. bias changes the depletion of carriers in the semiconductor and thus the total capacitance of the structure. The maximum capacitance of the MOS structure is obtained when the semiconductor is in accumulation and the total capacitance of the structure is the capacitance of the semiconductor surface oxide. The minimum capacitance is obtained when the semiconductor region under the tip is in inversion. Since SCM the output signal is proportional to the differential capacitance, to get a high signal we need to maximize the difference between the maximum and minimum in the total MOS capacitance.

Junction profiles of hot electron stressed high-voltage N-channel field effect transistor (NFET) devices were measured by scanning capacitance microscopy. Deactivation of phosphorous was observed on the drain side. To directly establish a link between phosphorus deactivation and hydrogen, junction profiles were measured on an unstressed NFET (N-type metal-oxide-semiconductor) device with and without H2 plasma treatment and with subsequent 400 °C annealing in helium. Phosphorus deactivation was observed in the device after H2 plasma treatment, while subsequent 400 °C annealing led to dissociation of the P–H (or H–Si–P) bond and recovery of the device junctions.

Electrical current at micro-/macro-scale of undoped and nitrogen-doped MWPECVD diamond films

The surface morphology and the electrical activation of P+ implanted 4H-SiC were investigated with respect to annealing treatments that differ only for the heating rate. P+ implantation was carried out in lightly doped n-type epitaxial layers. The implantation temperature was 300 °C. The computed P profile was 250 nm thick with a concentration of 1×1020 cm-3. Two samples underwent annealing at 1400 °C in argon with different constant ramp up rates equal to 0.05° C/s and 40 °C/s. A third sample underwent an incoherent light Rapid Thermal Annealing (RTA) at 1100 °C in argon before the annealing at 1400 °C with the lower ramp rate. The ramp up of the RTA process is a few hundred degrees per second. Atomic Force Microscopy (AFM) micrographs pointed out that the surface roughness of the samples annealed at 1400 °C increases with increasing heating rate and that the critical temperature for surface roughening is above 1100 °C. Independently on the annealing cycle, Scanning Capacitance Microscopy (SCM) measurements showed that the P profiles are uniform over the implantation thickness and have plateau concentration around 9×1018 cm-3 in all the implanted samples. The fraction of P atoms activated as donors is 13% of the total implanted fluence.

In this paper we investigate the dopant quantification error introduced in scanning capacitance microscopy measurements by the nonlinearity of the capacitance-to-voltage characteristic of MOS structures. The C-V response of the measurement set up is derived by finite element simulation and the systematic error introduced by signal processing is quantified by harmonic distortion analysis. It is shown that the investigated effect can lead to a systematic overestimate of the dopant concentration ranging from a factor of 2 up to a factor of 20, depending on the experimental conditions.

The advantages of scanning capacitance microscopy (SCM) in observing Fe–Zn interdiffusion of an electro-absorption (EA) modulator and the relationship between the interdiffusion and device characteristics are discussed. SCM images show that there is a Zn diffusion region, in which the semi-insulating region is converted into p-type due to Zn diffusion, on both sides of the mesa and the Zn diffusion region becomes smaller as the Fe doping concentration is reduced. By comparison, scanning electron microscopy (SEM) images captured after stain etching of EA modulators did not clearly delineate the Zn diffusion front. The influence of a ruthenium (Ru)-doped InP burying layer on the interdiffusion has also been investigated by SCM. These results indicate that in order to improve the performance of EA modulators, it is important to prevent Zn diffusion into the semi-insulating layers.

Background . Noise pollution is a burden exerting a harmful and irritating effect on human health. Children are particularly sensitive to noise burden. In this connection, it is especially important to control the noise pollution level in public education organizations where children spend significant time. Objective . The study is aimed at determining objective and subjective parameters of noise pollution in public education organizations based on the analysis of data obtained by measuring noise levels in school campuses in Saransk and directly in classrooms, as well as by questioning the teachers of these schools. Methods . The measurement of noise burden was carried out in 10 schools using the noise and vibration level meter “Assistant” with class I accuracy. Noise measurements in school campuses and classrooms were performed in accordance with the GOST 23337-2014 requirements. Assessment of results was conducted in accordance with sanitary standards 2.2.4/2.1.8.562-96 “Noise in the workplace, residential and public buildings and housing developments”. Results . Based on noise measurement results, the highest noise levels were found in school № 2 (65.5 dBА on the campus, 51.2 dBA in the classroom) which is located in the center of a traffic interchange. The lowest noise parameters were found in school № 35 (45.2 dBА on the campus, 37.7 dBА in the classroom) which is located in the residential quarter quite far away (242-321 m) from the main source of noise, the motorway. Conclusion . Study results attest that maximum noise levels at school campuses do not exceed the permissible exposure limit of 70 dBA. In all schools noise values conform to the noise standards (maximum sound pressure level in classrooms did not exceed 55 dBA).

High lift devices, together with landing gears, are the main sources of airframe noise during the approach‐and‐landing phase of aircraft flight. Typical high lift devices include leading edge slats and trailing edge flaps. Other high‐lift‐related noise‐generating devices include spoilers if deployed during a steep approach operation. All the above aerodynamic devices are retracted during the cruise phase of aircraft operation. A slat, when deployed, forms a cove region between the slat and the central main element of the aircraft wing. Flow separation, flow recirculation, an unsteady shear layer, and slat settings together generate noise of mainly broadband content. For a flap, the outboard flap side edge and vortex system associated with it are the main sources of noise. The intensity of high lift device noise generally follows a power law of flow velocity. The main sources of noise are identified and described in this chapter. Introduction is provided concerning main semi‐empirical and computational fluid dynamics methods. Noise attenuation methods are also described.