Observation of metal–oxide–semiconductor transistor operation using scanning capacitance microscopy

Scanning capacitance microscope (SCM) images, and the two-dimensional (2D) dopant profiles extracted from them, show poor reproducibility from laboratory to laboratory. Major factors contributing to SCM image variability include: poor sample surface and oxide quality, excess carrier generation from stray light, reduced sensor dynamic range from stray capacitance, and use of nonoptimal SCM operating voltages. This article discusses the sources of SCM image variability, how they affect the measured SCM images, and possible approaches for mitigating their effects. Recommended procedures for extracting quantitative 2D are discussed. Finally, a set of informal research materials is introduced consisting of a complementary metal-oxide-semiconductor transistor pair, an identical pair without metallization, and a pair of transistor-like structures with the conductivity type of the source/drains reversed. These structures are intended for use with the FASTC2D software to help improve laboratory-to-laboratory dopant profile reproducibility.

In order to demonstrate its unique capabilities, a combined microscope comprised of a scanning capacitance microscope and a contact mode atomic force microscope was used to image a buried structure. The atomic force microscopy images surface topography, while the scanning capacitance microscope simultaneously images buried structure. By applying a modulation technique, the voltage derivative of the capacitance (dC/dV) was used as a scanning capacitance microscope signal. The sample used for the demonstration was a silicon wafer with metal lines 4 nm in thickness covered by a 40-nm-thick layer of silicon oxide. The scanning capacitance microscope image was dependent on the bias voltage applied to the probe and the sample. Since the scanning capacitance microscope signal above the metal lines is zero, the bias voltage dependency of the contrast in scanning capacitance microscope images corresponds directly to the scanning capacitance microscope signal versus V at locations where the metal line is not buried. However, the bias dependency of the contrast did not agree with the scanning capacitance microscope signal observed between metal lines. A possible mechanism for the discrepancy between these bias dependencies is discussed based upon charge deposition on the sample surface caused by tip contact and lateral movement of the charges in the adsorbed water on the sample surface.

Scanning capacitance microscopy (SCM) is a powerful tool for two-dimensional (2D) dopant/carrier profiling. Currently noise limits the accuracy of 2D dopant profiles obtained by SCM. In an effort to reduce noise, a systematic analysis of different SCM noise sources is provided. The main noise sources during SCM measurements are capacitance sensor noise and oxide–semiconductor surface induced noise. For adequate tip size, the dominant noise in SCM measurements is caused by variations in the quality of surface. On as-polished surfaces, nonstationary noise is observed. This noise is likely caused by the variations in the density of oxide traps. Tip induced charging of these traps and local variations or fluctuations in discharge time during SCM imaging cause the noise level and noise pattern to be different from image to image. Heat treatment under ultraviolet irradiation or in a hydrogen ambient is found to be an effective way to reduce or even eliminate this type of SCM noise. Stationary surface noise is mostly created by the variations in the oxide thickness. This type of noise correlates with topographic roughness and is very consistent during SCM measurements. By reducing the topographic roughness, the stationary surface noise may be reduced to the level of ∼10−2 of the depletion SCM signal for typical experimental conditions. It is shown that the capacitance sensor noise depends on the capacitance sensor tuning parameters and under proper conditions can be reduced to a negligible level for standard probe tips used in SCM measurements.

Scanning capacitance microscopy (SCM) has been applied to microscopic characterization of electrical properties of silicon-on-insulator (SOI) wafers. Two kinds of capacitance-voltage (C-V) methods have been proposed for separately characterizing the electrical properties of a gate oxide, an SOI layer, a buried oxide (BOX) layer. a Si substrate, and their interfaces: (i) a front-gate C-V method whereby the electrical properties of the gate oxide and front SOI (the gate oxide/SOI) interface can be characterized. arid (ii) a back-gate C-V method for the characterization of the electrical properties of the BOX layer. back SOI (the BOX/SOI) interface, and the BOX/Si substrate interface. Furthermore, SCM images of the sampled SOI wafer have been obtained for visualizing the microscopic spatial distribution of electrical properties of SOI wafers by using the proposed C-V methods. These SCM images revealed the fluctuation in tile oxide charges arid interface traps. SCM has been demonstrated to be an effective tool for microscopic electrical characterization of SOI wafers.

Scanning capacitance microscopy (SCM) is currently one of the most promising tools for twodimensional carrier profiling. This technique, based upon atomic force microscope (AFM) operated in the contact mode, uses a conductive probe which is scanned over the semiconductor surface. The conductive probe, oxide on the surface of the semiconductor, and the semiconductor substrate form a metal-oxide-semiconductor (MOS) structure. An a.c. bias is applied to the tip and the capacitance of the MOS structure is monitored. The a.c. bias changes the depletion of carriers in the semiconductor and thus the total capacitance of the structure. The maximum capacitance of the MOS structure is obtained when the semiconductor is in accumulation and the total capacitance of the structure is the capacitance of the semiconductor surface oxide. The minimum capacitance is obtained when the semiconductor region under the tip is in inversion. Since SCM the output signal is proportional to the differential capacitance, to get a high signal we need to maximize the difference between the maximum and minimum in the total MOS capacitance.

Junction profiles of hot electron stressed high-voltage N-channel field effect transistor (NFET) devices were measured by scanning capacitance microscopy. Deactivation of phosphorous was observed on the drain side. To directly establish a link between phosphorus deactivation and hydrogen, junction profiles were measured on an unstressed NFET (N-type metal-oxide-semiconductor) device with and without H2 plasma treatment and with subsequent 400 °C annealing in helium. Phosphorus deactivation was observed in the device after H2 plasma treatment, while subsequent 400 °C annealing led to dissociation of the P–H (or H–Si–P) bond and recovery of the device junctions.

Electrical current at micro-/macro-scale of undoped and nitrogen-doped MWPECVD diamond films

The advantages of scanning capacitance microscopy (SCM) in observing Fe–Zn interdiffusion of an electro-absorption (EA) modulator and the relationship between the interdiffusion and device characteristics are discussed. SCM images show that there is a Zn diffusion region, in which the semi-insulating region is converted into p-type due to Zn diffusion, on both sides of the mesa and the Zn diffusion region becomes smaller as the Fe doping concentration is reduced. By comparison, scanning electron microscopy (SEM) images captured after stain etching of EA modulators did not clearly delineate the Zn diffusion front. The influence of a ruthenium (Ru)-doped InP burying layer on the interdiffusion has also been investigated by SCM. These results indicate that in order to improve the performance of EA modulators, it is important to prevent Zn diffusion into the semi-insulating layers.

In this article, we present a new one-dimensional (1D) dopant profile determination method, which extends to the quantitative three-dimensional (3D) dopant profile extraction. This nondestructive method, which is different from the common scanning capacitance microscopy (SCM) measurement/dopant extraction, can potentially measure real metal–oxide–semiconductor field-effect transistor devices having 3D structure. Through SCM modeling, we found that the depletion layer in silicon was of a form of a spherical capacitor with the SCM tip biased. Two-dimensional (2D) finite differential method code with a successive over relaxation (SOR) solver has been developed to model the measurements by SCM of a semiconductor wafer that contains an ion-implanted impurity region. Then, we theoretically analyzed the spherical capacitor and determined the total depleted-volume charge Q, capacitance C, and the rate of capacitance change with bias dC/dV. It is very important to observe the depleted carriers’ movement in the silicon layer by applying the bias to the tip. So, we calculated the depleted-volume charge, considering different factors such as tip size, oxide thickness, and applied bias (dc+ac), which have an influence on potential and depletion charges. Finally, we developed a 1D inversion algorithm to convert the SCM output (dC/dV) into real dopant concentration, comparing the SCM signal output with the calculated dC/dV. Using the inversion modeling, we have quantitatively extracted the 1D dopant profile from the SCM dC/dV vs V curves.

Scanning capacitance microscopy (SCM) using a dV/dC signal has been proposed for local mapping of interface traps in an insulator/semiconductor structure. In conventional SCM measurements using a dC/dV signal, it is difficult to accurately analyze the spatial distribution of interface traps from the obtained SCM images because the dC/dV signal is inversely proportional to the interface trap density. In the proposed technique, however, the spatial distribution of the interface traps can be characterized using the dV/dC signal, which is directly proportional to the interface trap density. The effectiveness of the proposed technique has been demonstrated by characterizing the spatial distributions of the interface traps in HfSiO/Si structures before and after H2 annealing. The dV/dC images obtained reveal that the spatial variation in the interface trap density is reduced by H2 annealing. Consequently, SCM measurements using a dV/dC signal have been verified to effectively characterize the spatial distribution of interface traps.

We report the operation of 12-nm-thick, (110)-oriented Ge-on-insulator p-channel metal–oxide–semiconductor field-effect transistors along <110> channel direction [(110)/<110> GOI pMOSFETs], fabricated by the Ge condensation technique. The device operation under the accumulation mode was observed with the back gate structure. (110)/<110> GOI pMOSFETs have exhibited 2.3 times higher effective hole mobility, comparing with (100)-oriented GOI control devices (µeffGOI(100)). Also, present devices have the hole mobility enhancement factor of 3.0 and 1.5 against the (100)-oriented Si universal hole mobility and the (110)-oriented Si-on-insulator (SOI) effective hole mobility, respectively. These results demonstrate the superior hole transport properties of (110)/<110> GOI pMOSFETs.

A unique and simple method is demonstrated for characterizing the electrical behavior of a single stacking fault in thin-film fully depleted silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFETs). SOI islands were created using selective epitaxial growth/epitaxial lateral overgrowth technology. P-channel MOSFETs, with the presence of a single stacking fault entirely in the channel region, were measured. The influence of a single stacking fault on device current–voltage characteristics was determined and compared to that of nearby identical devices without stacking faults. It was found that the threshold voltage increased and saturation current decreased, but had low subthreshold leakages. P-channel MOSFETs, with a single stacking fault crossing the gate and penetrating into the source and drain, had high subthreshold leakage currents.

The influence of gamma-radiation on the electrical characteristics of 6H–SiC p-channel metal–oxide–semiconductor field effect transistors (MOSFETs) containing step bunching is reported. The formation of step bunching perpendicular to the channel inhibited the current flow, whereas such an effect was not seen in devices with step bunching formed parallel to the channel. The effective channel mobility in the latter devices increases with gamma-radiation. This improvement of the hole mobility is attributed partially to the positively trapped charges screened the holes from approaching too close to the surface and partially to the effect of position of these charges, resulting in a reduction of scattering and capture of holes. No enhancement in the effective channel mobility was observed for devices with no step bunching or with root mean square roughness in the channel region less than 4 nm. Further irradiation leads to a decrease in the effective channel mobility due to both the formation of latent interface traps and electrostatics repulsion of holes.

Correcting scanning capacitance microscope images for the effect of surface gradient

The temperature and drain current (ID) dependencies of sub-threshold swing (SS) values of Si n- and p-channel metal–oxide–semiconductor field effect transistors (MOSFETs) with different substrate impurity concentrations ranging from the 1015 to 1018 cm−3 ranges are systematically and experimentally evaluated at cryogenic temperatures. It is found that SS of p-channel MOSFETs tends to increase with decreasing temperature, which contrasts with saturation of SS of n-MOSFETs at cryogenic temperatures, well reported by many previous works. To explain these SS behaviors quantitatively, we employ a density-of-state (DOS) model with tail states consisting of localized states in a deep energy range and mobile states in a shallow energy range, which are attributable to potential fluctuations caused by substrate impurities. It is shown that this model can quantitatively explain the temperature and ID dependencies of SS of both n-MOSFETs and p-MOSFETs. Then, we are assuming that the Si p-MOSFET has a higher density of localized states than the n-MOSFET. Thus, the increase in SS of the p-MOSFETs with decreasing temperature is explained by an increase in the density of localized states at the Fermi level with decreasing temperature, because the density of localized states increases with elevating the Fermi level position in the employed DOS model.