SEM based data extraction for model calibration

Classical SEM metrology, CD-SEM, uses low data rate and extensive frame-averaging technique to achieve high-quality SEM imaging for high-precision metrology. The drawbacks include prolonged data collection time and larger photoresist shrinkage due to excess electron dosage. This paper will introduce a novel e-beam metrology system based on a high data rate, large probe current, and ultra-low noise electron optics design. At the same level of metrology precision, this high speed e-beam metrology system could significantly shorten data collection time and reduce electron dosage. In this work, the data collection speed is higher than 7,000 images per hr. Moreover, a novel large field of view (LFOV) capability at high resolution was enabled by an advanced electron deflection system design. The area coverage by LFOV is >100x larger than classical SEM. Superior metrology precision throughout the whole image has been achieved, and high quality metrology data could be extracted from full field. This new capability on metrology will further improve metrology data collection speed to support the need for large volume of metrology data from OPC model calibration of next generation technology. The shrinking EPE (Edge Placement Error) budget places more stringent requirement on OPC model accuracy, which is increasingly limited by metrology errors. In the current practice of metrology data collection and data processing to model calibration flow, CD-SEM throughput becomes a bottleneck that limits the amount of metrology measurements available for OPC model calibration, impacting pattern coverage and model accuracy especially for 2D pattern prediction. To address the trade-off in metrology sampling and model accuracy constrained by the cycle time requirement, this paper employs the high speed e-beam metrology system and a new computational software solution to take full advantage of the large volume data and significantly reduce both systematic and random metrology errors. The new computational software enables users to generate large quantity of highly accurate EP (Edge Placement) gauges and significantly improve design pattern coverage with up to 5X gain in model prediction accuracy on complex 2D patterns. Overall, this work showed >2x improvement in OPC model accuracy at a faster model turn-around time.

As the essential techniques for the CD (Critical Dimension) measurement of the LCD pattern, there are various modules such as an optics design, auto-focus [1-4], and precise edge detection. Since the operation of image enhancement to improve the CD measurement repeatability, a ring type of the reflected lighting optics is devised. It has a simpler structure than the transmission light optics, but it delivers the same output. The edge detection is the most essential function of the CD measurements. The CD measurement is a vital inspection for LCDs [5-6] and semiconductors [7-8] to improve the production yield rate, there are numbers of techniques to measure the CD. So in this study, a new subpixel algorithm is developed through facet modeling, which complements the previous sub-pixel edge detection algorithm. Currently this CD measurement system is being used in LCD manufacturing systems for repeatability of less than 30 nm.

Optical proximity correction (OPC) plays a vital role in the lithography process of cutting-edge IC fabrication. The quality of lithography models used in OPC is fundamental to the final performance of the OPC in production. Traditionally, two-dimensional proximity features such as line-end, bar-to-bar or bar-to-line were only partially characterized because of the difficulty in transferring the SEM information into the OPC model building process. A new methodology of edge placement error (EPE) measurement using CD-SEM is proposed as part of an OPC model building and process/OPC qualification flow. It is not easy to generate EPE measurements because of the inherent need to overlay the design and the SEM in order to quantify EPE. The quality of the EPE measurement depends on both the accuracy of the SEM image scan rotation and magnification, but also on the accuracy of pattern matching between the design layout pattern and the realized pattern (wafer). These problems do not exist in simulation, but model calibration requires a direct comparison between simulation and measurement. Measuring EPE effectively brings the measurement information into the realm of the design. Hitachi High-Technologies has developed a "fully automated EPE measurement function" based on design layout and detected edges of SEM image as a solution to this issue. This study shows several practical evaluation results using the automated EPE measurement function. The applications that will be discussed are as follows. 1) Design based classification of edges and subsequent quantification of SEM EPE for many types of edge arrangement and orientation. In this study, we will examine line-end-adjacent, line-end, corner, and other critical gate edges. 2) SEM image based classification of EPE fliers as a new population of errors. 3) Comparison between the detected edge of the feature within the SEM image and a polygon shape generated by lithography simulation to determine the quality of the simulation. 4) Conversion of the SEM image edge contour into an OASIS file and construction of a process variability band to quantify CD variability for all 2D contexts in a SEM image.

Traditionally, lithography critical dimension (CD) measurements with stepper de-focus and deltas in sidewall angle do not correlate well with the ultimate product measurement, namely electrical performance. It is important in etch bias control, therefore, to control more than just the physical CD. It is at a minimum, important to show how the changes in sidewall angle control at lithography relate to etch biases. This is especially important as chip geometries shrink, and the size and shape of the sidewall becomes a larger portion of the line width geometry. This makes precise CD measurements coupled with slope angle measurements, in real time, important to process control in lithography so that ultimately the desired dimension is achieved at the post etch step, and therefore electrical performance can be gauged. We will present data taken from Focus/Exposure Matrices in the form of CD measurements, in-line sidewall angle reconstruction, and electrical measurements. We hope to correlate electrical performance to post develop CD and slope sidewall angle as measured without destructive cross sections.

The dispositioning of mask defects must also heed the increasing gap between the lithography wavelength and wafer-feature widths. For the larger technology nodes, where printed-wafer shapes are similar to those on the mask, mask-level analysis is sufficient. However, for smaller nodes, wafer-level scoring is useful since every defect does not significantly impact the wafer. Wafer-level analysis often relies on measurements of critical dimension (CD). However, as reticle enhancement technology proliferates, there are increasingly more curved edges where CD cannot be used. For example, false alarms can result from measuring CD near line ends because slight variations in measurement position may produce large CD changes. More importantly, a killer defect may be missed if cutlines are forbidden near line ends because the CD measurements are too far from the defect. Wherever CD measurements are not advisable, we advocate the use of Area scoring by computing the difference in printed feature area. We are not abandoning CD scoring but rather combining it with Area scoring, and using the more pessimistic score. For Area scoring, we use (Defect area - Reference area)/(Reference area). In general, the reference area is difficult to define since many shapes are not easily parsed into primitive shapes. Therefore, we use a square of side equal to the target CD. This square defines the window for a sliding-window average of the area difference. The maximum average value is then chosen from the entire image. Unlike Edge Placement Error, Area is sensitive to long, thin difference regions. Unlike Flux or Maximum Intensity Difference, Area is threshold-aware; it measures what prints and shows process-window variation.

The Hitachi Model S-6280 high resolution field emission Scanning Electron Microscope (SEM) is used at Motorola's MOS-12 facility for Critical Dimension (CD) measurements of less than 1 micrometer in size. This tool is used to measure 200-mm diameter wafers with a low accelerating voltage in the range 0.7-1.0 kV. During new process development the tool is run in both manual mode and in a fully automated mode utilizing patten recognition for global alignment as well as feature CD measurement. Results on the reproducibility of fully- automated measurements show that this technique provides a significantly improved measurement capability compared to the standard manual technique.

As CMOS feature size scales down to 65nm and below, challenges for device and circuit manufacturability are emerging. As commonly seen in real designs, devices with distorted gate shapes and rough line-edges are manufactured despite the applications of aggressive resolution enhancement techniques (RET). It has been shown that such irregular gates could introduce significant extra leakage current. Existing tools and device models cannot handle non-rectangular geometries. Therefore, it is critical that a modeling flow capable of handling such irregular devices is developed and smoothly integrated into the post-lithography delay and leakage circuit analysis process. Previously proposed methods either model an irregular transistor as two different rectangular devices, one for on and the other for off state analyses; or they are difficult to be implemented. In this paper, we propose a new modeling approach that serves as a fast and simple solution to this problem and overcomes these drawbacks. We found that by adjusting both gate length and width of the equivalent device, a single equivalent rectangular device can be determined. Through TCAD and SPICE simulation experiments, we demonstrate that our model can accurately capture both on and off currents of the modeled nonrectangular gate device. The average error of our modeling approach is 1.6% for I_on and 7.5% for I_off.

Optical proximity correction (OPC) plays a vital role in the lithography process development of current semiconductor devices. OPC is utilized to achieve the ideal pattern shape because of the limitations of optical resolution. However, the lithography process design has become increasingly more complex due to the abundant use of OPC features. Hence, metrology requests for CD-SEM have also become more complex and diverse in order to characterize the critical OPC models. The number of measurement points for OPC model evaluation has increased to several hundred points per layer, and metrology requests for realized pattern shapes on the wafer are no longer simple one-dimensional measurements. Metrology requests include not only the traditional line width measurements, but also edge placement error (EPE) and corner rounding to identify line end shortening. Several researchers have proposed using the design layout as a template instead of the SEM image for the recipe creation of CD-SEM and EPE measurement. However, it is very difficult to achieve good matching results between the design layout and the SEM image in practical processing times. Hitachi High-Technologies has developed a robust and quick matching engine between the design layout and SEM image bitmap. The new system, incorporating this new matching engine, can automatically create a practical recipe from the coordinate information of measurement point and the design layout information, such as GDSII. As a result, the new system can vastly reduce the amount of time and number of operations required to generate a several-hundred point CD-SEM recipe for OPC evaluation. This study demonstrates the capability and presents evaluation results of this new matching engine. This new capability has proven to be a viable solution for OPC evaluation, and its efficiency will allow for quicker information turns between design and manufacturing.

With continued aggressive process scaling in the subwavelength lithographic regime, resolution enhancement techniques (RET) such as optical proximity correction (OPC) are an integral part of the design to mask flow. OPC adds complex features to the layout, resulting in mask data volume explosion and increased mask costs. Traditionally the mask flow has suffered from a lack of design information, such that all features (whether critical or non-critical) are treated alike by RET insertion. Gupta et al. (2003) proposes to exploit design information (timing slacks) to reduce OPC data volume, but has a number of impractical aspects. In this paper, we propose an implementable flow that drives model-based OPC explicitly by timing constraints, with the objective of reducing mask data volume and OPC runtime. We apply a mathematical programming based slack budgeting algorithm to determine edge placement error (EPE) tolerance budgets for all polysilicon gate geometries. These tolerances are then enforced by a commercial OPC tool to achieve up to 24% MEBES data volume and 41% OPC runtime reductions on a suite of six testcases implemented in Artisan TSMC 0.13 /spl mu/m libraries.

In modern VLSI design flow, subresolution assist feature (SRAF) insertion is one of the resolution enhancement techniques (RETs) to improve chip manufacturing yield. With aggressive feature size continuously scaling down, layout feature learning becomes extremely critical. In this article, for the first time, we enhance conventional manual feature construction, by proposing a supervised online dictionary learning algorithm for simultaneous feature extraction and dimensionality reduction. By taking advantage of label information, the proposed dictionary learning framework can discriminatively and accurately represent the input data. We further consider SRAF design rules in a global view, and design two integer linear programming models in the post-processing stage of SRAF insertion framework. The experimental results demonstrate that, compared with a state-of-the-art SRAF insertion tool, our framework not only boosts the performance of the machine learning model but also improves the mask optimization quality in terms of edge placement error (EPE) and process variation (PV) band area.

The requirements for advanced lithography solutions are constantly increasing. Up to now the optical lithography with its extension into the immersion lithography and strong resolution enhancement techniques (RET) represents the lithography solution of choice. With decreasing critical dimensions (CD) new approaches are needed to provide cost effective methods for small and medium volume production on one side and for efficient photomask fabrication including the RET on the other side. A viable solution for both application fields is the Multi Shaped Beam (MSB) technology, which is currently being developed at Vistec Electron Beam in Jena. E-beam technology has already been used for R&D as well as prototyping applications well ahead of the respective production technology node. It is as well the technology of choice for the future mask fabrication. However, the decreasing CD and thus increasing pattern density asks for new ideas to overcome the throughput challenges faced today. This bottleneck is addressed by parallel writing methods where MSB is one of these techniques. In correlation with the MSB writing technology an appropriate data preparation path is mandatory. One major criterion for the performance of MSB data processing is the shot count reduction which can be reached for different types of patterns. In this paper results from an analysis of the current status of MSB shot segmentation are reported. Beside collecting statistical data of the individual structure size distribution an analysis of the shot count on different pattern coming from mask write as well as direct write applications was carried out. This was performed for different technology nodes and the results are compared.

With continuous shrinking technology nodes, the error tolerances for mask CD (critical dimension) becomes tighter and tighter since mask errors are passed on downstream and might even be amplified at wafer level. Therefore, high accuracy MPC (Mask Process Correction) models are imperative. Besides the mask model, the MPC algorithm for the input layout also has a critical influence on mask quality. This paper studies and compares two methods of MPC correction: a new method, introducing a correction algorithm based on the CD-SEM box is compared to the standard method that measures EPE (edge placement error) only at the center of an edge. Under which condition the EPE measurement method for MPC correction by the CD-SEM box method should be applied is discussed and its influence on the correction accuracy of small CD patterns is demonstrated.

Lack of precision and accuracy of in-process critical dimension (CD) measurements of linewidth continues to be a serious problem at micrometer and submicrometer dimensions. Even with highly repeatable optical linewidth measurement systems, variable "offsets" or errors have been shown to occur with changes in process variables such as thickness of the patterned layer and sublayers and changes in the indices of refraction of the materials. All of these variations result in changes in the optical phase difference which occurs on reflection at the line edge and, therefore, results in changes in the structure of the optical image. Although an accurate coherent optical edge detection method has been developed, it requires accurate knowledge of the phase difference which is not always possible in CD measurements. This paper proposes a new dual-threshold method for edge detection and focusing, based on image theory, which can be adapted to most optical microscope-based measurement systems. It does not require knowledge of the phase difference at the line edge. The accuracy of this criterion is compared to two more widely used criteria, (1) the minimum and (2) 50% threshold, and it is concluded that, when the phase difference is unknown and varies with normal processing, the new dual-threshold method is the superior method.

Introduction and problem statement Given that EUV lithography allows printing smaller Critical Dimension (CD) features, it can result in non-normal distributed CD populations on ADI wafers [Civay SPIE AL 2014], leading to errors in predicted failure rates [Bristol SPIE AL 2017]. As a result, there is a need to quantify the actual behavior of the CD population extremes by means of massive metrology [Dillen EUVL 2018]. Not only allows this to study the CD distribution, we can in parallel also evaluate pattern quality and the failure mechanisms leading to defects. This massive metrology method provides an accurate failure rate based on CD, and enables new possibilities to define a failure rate based on different metrics in a single measurement. Method We analyze the CD uniformity of pillars in polar coordinates using a global waveform based thresholding strategy. In conjunction with this CD information, we also evaluated the print quality of each individual measured feature. Fig 1. In line detected anomalies and failure definitions As we gather this information during the measurement of CD, we can limit the additional measurement overhead to neglectable levels. Application and outlook We will show how we can leverage this to determine a defect based process window and relations of failure mechanisms through process conditions (see figure 2). When we take failures in a CH dataset into account, we illustrate the effect on the shape of a large dataset distribution in figure 3. Fig 2. Defect identification for a through exposure dose experiment of pillars. For each condition >13k pillars where measured. The plot clearly shows an asymmetric behavior due to different failure mechanisms at low and high energy. The 2 vertical lines at relative energies 0.93 and 1.05 times nominal indicate the low defect process window. Fig 3. A distribution of measured regular grid dense CH. The red line is the unfiltered CD data, the blue line is the shape of the distribution after filtering individual CH measurements that have a much lower contrast than expected.

OPC (Optical Proximity Correction) improves the feature CD (critical dimension) uniformity and pattern fidelity in general. However, since model calibration only takes CD measurements at optimum exposure dose and best focus condition, the correction result may not be desirable at non-optimum conditions due to significant sub-resolution process distortion. Certain specific patterns are prone to bridging or pinching (we refer this type of location as hotspot in this paper) when process drifts a little from optimum condition. Simulation based full-chip verification became the method of choice for capturing hotspots on post-OPC layouts prior to mask tape-out to save development time and cost. In this paper, a complete simulation and analysis flow using SiVL was experimented to capture hotspots for a 100nm node process. Calibrated process model and multiple optical models with different focus/threshold conditions were applied for simulation. The method and effectiveness of filtering and analyzing fatal errors from output error database was discussed. The analysis results were then correlated to actual wafer printing. A good match between prediction and experiment was found.