Multi-shaped beam data preparation

In this paper a full package high throughput multi electron-beam approach, called Multi Shaped Beam (MSB), for applications in mask making as well as direct write will be presented including complex proof-of-lithography results. The basic concept enables a significant exposure shot count reduction for advanced patterns compared to standard Variable Shaped Beam (VSB) systems and allows full pattern flexibility by concurrently using MSB, VSB and Cell Projection (CP). Proof of lithography results will be presented, which have been performed using a fully operational electron-beam lithography system including data path and substrate scanning by x/y-stage movement.

At the EMLC 2009 in Dresden the data preparation package ePLACE was already presented. This package has been used for quite different applications covering mask write, direct write and special applications. In this paper we will disclose results achieved when using the ePLACE package for processing of layout data of immediate interest. During the evaluation phase of the new solution we could benefit from broad experience we collected over many years with the fracture performance of the MGS software, which is one core element of today's ePLACE package. A key interest of this paper is the investigation of the scalability of computing solutions as a cost-effective approach when processing huge data volumes with the new solution. This is reflected against current state-of-the-art data processing tasks being part of both mask write and direct write applications. Furthermore, we evaluated visualization and simulation possibilities of the ePLACE package with respect to its use with latest layouts in various applications. The improved performance of the data preparation package including its adaptation to new e-beam lithography options, as, for instance, the incorporation of the cell projection capability or the newly developed Multi Shaped Beam (MSB) technology, will be also discussed. As an example the matching of the data path with a Vistec SB3055 will be outlined. Processing of Design For E-Beam (DFEB) data (including cell contents) and their conversion to real exposure data is reported. The advantages of the parallel use of standard shaped beam und cell projection technologies are highlighted focussing on latest writing time yields achieved when applying the CP feature.

As new resolution enhancement techniques (RETs) are adopted to progress beyond 100 nm, the costs and benefits to the overall system of data handling must be viewed as an overall system. A 'state' approach to viewing flows has been very useful for determining insertion points for several RETs. Data preparation is a necessary part of the transformation from layout to mask. The data manipulations of required for RET also fall in this space between layout and mask. When separate point tools are used to carry out these different manipulations, increasingly large amounts of time are required to simply move data from one point tool to the other. As data file sizes increase as expected over the next decade, this problem will increase by orders of magnitude. None of this time is providing any additional productivity for data preparation. The result has been pressure to provide an integrated solution, in which OPC, phase assignment, and data preparation all share a single database. This delays flattening the data until the last necessary moment, presumably in the mask writer itself.

In order to maintain manageable process windows, mask shapes at the 20nm technology node and below become so complex that mask write times reach 40 hours or might not be writeable at all since the extrapolated write time reaches 80 hours. The recently introduced Model Based Mask Data Preparation (MB-MDP) technique is able to reduce shot count and therefore mask write time by using overlapping shots. Depending on the amount of shot count reduction the contour of the mask shapes is changed leading to the question how the mask contour influences wafer performance. This paper investigates the tradeoff between mask shot count reduction using MB-MDP and wafer performance using lithography simulation. A typical Source-Mask-Optimization (SMO) result for a 20nm technology will be used as an example.

With the technology node entering 45nm and below and the delay of the EUV lithography, the resolution enhancement techniques (RET) has been considered indispensable to extend the life time of conventional 193nm lithography. Traditional RETs, for example, optical proximity correction (OPC), phase-shifting mask (PSM), inverse lithography technique (ILT) and so on, use a fixed source thus limiting the degrees of freedom during the mask pattern optimization. To overcome the restriction, recently, source and mask co-optimization (SMO) has been proposed as a strong contender in RET. However, SMO is very computationally intensive. To mitigate the issue, we adopt a method which has demonstrated in good effectivity and efficiency in illumination source optimization. Based on the gray-level pixel based source representation, the gradient of the cost function is calculated to guide optimization to improve the wafer image fidelity and depth of focus (DOF). Moreover, the similar method has been used in mask optimization to form a complete SMO algorithm. The SMO algorithm is demonstrated using two mask patterns with critical dimension (CD) of 45nm, including a periodic array of contact holes and a tri-bar pattern. Both the results showed high image quality have been achieved using our SMO algorithm.

The model calibration process, in a resolution enhancement technique (RET) flow, is one of the most critical steps towards building an accurate OPC recipe. RET simulation platforms use models for predicting latent images in the wafer due to exposure of different design layouts. Accurate models can precisely capture the proximity effects for the lithographic process and help RET engineers build the proper recipes to obtain high yield. To calibrate OPC models, test geometries are created and exposed through the lithography environment that we want to model, and metrology data are collected for these geometries. This data is then used to tune or calibrate the model parameters. Metrology tools usually provide critical dimension (CD) data and not edge placement error (EPE - the displacement between the polygon and resist edge) data however model calibration requires EPE data for simulation. To work around this problem, only symmetrical geometries are used since, having this constraint, EPE can be easily extracted from CD measurements. In real designs, it is more likely to encounter asymmetrical structures as well as complex 2D structures that cannot easily be made symmetrical, especially when we talk about technology nodes for 65nm and beyond. The absence of 2D and asymmetric test structures in the calibration process would require models to interpolate or extrapolate the EPE's for these structures in a real design. In this paper we present an approach to extract the EPE information from both SEM images and contours extracted by the metrology tools for structures on test wafers, and directly use them in the calibration of a 55nm poly process. These new EPE structures would now mimic the complexity of real 2D designs. Each of these structures can be individually weighed according to the data variance. Model accuracy is then compared to the conventional method of calibration using symmetrical data only. The paper also illustrates the ability of the new flow to extract more accurate measurement out of wafer data that are more immune to errors compared to the conventional method.

This industry faces new challenges every day. It gets tougher as process nodes shrink and the data complexity and volume increase. We are a mask data preparation (MDP) software provider, and have been providing MDP systems to mask shops since 1990. As the industry has, MDP software providers also have been facing new challenges over time, and the challenges get tougher as process nodes shrink and the data complexity and volume increase. We discuss such MDP challenges and solutions in this paper from a MDP software provider’s perspective. The data volume continuously increases, and it is caused by shrinking the process node. In addition, resolution enhancement techniques (RET) such as optical proximity correction (OPC) and inverse lithography technique (ILT) induce data complexity, and it contributes considerably to the increase in data volume. The growth of data volume and complexity brings challenges to MDP system, such as the computing speed, shot count, and mask process correction (MPC). New tools (especially mask writers) also bring new challenges. Variable-shaped E-beam (VSB) mask writers demand fracturing less slivers and lower figure counts for CD accuracy and write time requirements respectively. Now multibeam mask writers are under development and will definitely bring new challenges.

As minimum feature sizes continue to shrink, patterned features have become significantly smaller than the wavelength of light used in optical lithography. As a result, the requirement for dimensional variation control, especially in critical dimension (CD) 3σ, has become more stringent. To meet these requirements, resolution enhancement techniques (RET) such as optical proximity correction (OPC) and phase shift mask (PSM) technology are applied. These approaches result in a substantial increase in mask costs and make the cost of ownership (COO) a key parameter in the comparison of lithography technologies. No concept of function is injected into the mask flow; that is, current OPC techniques are oblivious to the design intent. The entire layout is corrected uniformly with the same effort. We propose a novel minimum cost of correction (MinCorr) methodology to determine the level of correction for each layout feature such that prescribed parametric yield is attained. We highlight potential solutions to the MinCorr problem and give a simple mapping to traditional performance optimization. We conclude with experimental results showing the RET costs that can be saved while attaining a desired level of parametric yield.

Design weak points, or “hotspots” remain a leading issue in advanced lithography. These often lead to unexpected critical dimension (CD) behavior, degradation of process window and ultimately impact wafer yield. Industry technology development focus on hotspot detection has included full chip lithography simulation and machine learning-based hotspot analysis. Most recently, the machine learning approach is gaining attention because it is faster and more practical than lithography simulation-based hotspot detection. The machine learning case is a feedback approach based on previous known design hotspots. Conversely, the simulation method has the benefit of proactively detecting hotspots in a new design regardless of historical data. However, full chip simulation requires resources in calculating time, computing power and additional time-to-market that render it impractical in some scenarios. As design rules shrink, advanced mask designs have significantly increased in complexity due to Resolution Enhancement Techniques (RET) such as Source Mask Optimization (SMO), advanced Optical Proximity Correction (OPC) and high transmission attenuating mask films. This complicates hotspot detection by existing OPC verification tools or rigorous lithographic simulation with wafer resist model. These resultant complex mask geometries make OPC optimization and hotspot detection using post design very difficult. In this paper, we will demonstrate the limitation of traditional hotspot detection technology. Typical OPC tools use simple techniques such as single Gaussian approximations on the design, such as corner rounding, to take the mask process impact to the geometry into account. We will introduce a practical lithography hotspot identification method using mask process model. Mask model-based hotspot detection will be used to precisely identify lithography hotspots and will provide the information needed to improve hotspots’ lithographic performance.

Continuous shrinking of semiconductor manufacturing node requires smaller critical dimension (CD) and higher pattern density, but also a better control of pattern local variability such as local CD uniformity (CDU). Thus, improving the process stability has been shown to improve local variability. Shrinking makes also crucial to control the process-specific patterned defectivity, with a more demanding defect detection and removal effort, which will depend on the mask level and stack materials. Therefore, integrating a new process in a recently installed immersion lithography cluster requires a thorough study of the influence of the track parameters in the specific process flow, as well as the use of last generation optical defectivity inspection, review and classification tools. In this work, we present the main results in the cooptimization of CD control, CD uniformity and after development inspection (ADI) of defectivity in a PTD immersion lithography process. The mask used is a gate layer targeting 42nm dense lines using a trilayer with topcoat lithographic stack.

As the critical dimension (CD) scaling down to below 45nm node, the technique of immersion lithography has been the mainstream solution for advance devices' manufacturing. Compared to traditional dry lithographical processes, immersion lithography processes become more complicated and require more efforts in developments, especially in the defecivity. As reported in many papers, since topcoat (TC) or TC-less photo-resist (PR) in immersion processes have high surface contact angle (CA), It would introduce new types of defects dedicated for immersion lithography, such as micro-bubbles, water-mark, micro-bridge etc. However, the defectivity of hole-layer patterns in immersion processes has been a big challenge around, which lots of lithography engineers have been striving for. In this paper, we focus on the characterizations and improvement of hole patterns in TC-less immersion lithography. We investigated the impact of developing processes and rinse processes by splitting all key parameters. By analyzing above experimental results, we have got optimal solutions for the defectivity of our hole-layer patterns, and the underlying mechanism also have been discussed. The results of our study will be presented and discussed in our paper.

Optical lithography continues to be extended with shorter exposure wavelength and higher numerical aperture tools. Strong resolution enhancement techniques such as alternating aperture phase-shifting utilize 2-beam imaging to achieve effective spatial frequency doubling, high DOF, and ultralow k1. For these techniques, unpolarized light exposure latitude worsens significantly for tighter pitches and smaller linewidths. In addition, the mask error factor begins to become polarization-dependent. Due to vector interference effects, TE-polarized light (electric field polarized parallel to line) provides better imaging than TM-polarized light (electric field perpendicular to line). Suppression of TM-polarized light will therefore enable aggressive subwavelength imaging. In this paper, we apply rigorous electromagnetic simulations to evaluate the typical dimensions of photomask features in order for them to exhibit TM polarization suppression. Subwavelength absorbing features with high aspect ratio are one possible way of achieving adequate polarization selectivity on a photomask. TE polarization selectivity for darkfield binary and alternating aperture strong phase-shifting masks can also be achieved with the use of smaller spaces and/or thicker absorbers. Throughput is traded off against polarization selectivity since there is also significant absorption of TE-polarized light by the polarizing features. Polarization-selective imaging solutions based on thick Cr photomask blanks are presented.

Control of critical dimension (CD) and resist profile is increasingly important in low-k1 lithography, and becomes more difficult in thin resist processing due to the chemical interaction occurring at the resist surfaces. Implementation of immersion lithography will make the control even more challenging since more sources of chemical interaction can play a role, e.g. leaching of photo active material from the resist into the water, or diffusion of the water into the resist. Moreover, the contact of the liquid in the scanner showerhead with the wafer surface is a dynamic and local interaction, which needs to be understood and quantified, since variations in soak time are a possible source of intra-field and across wafer CD-variations. In this paper we developed a methodology to understand and to quantify the impact of immersion scanner soak on resist profile control and CD-control. The methodology is on the one hand based on the simulation of the showerhead movements over the wafer during the immersion lithography process, where for a particular location on the wafer the soak time is calculated by accumulating the interaction time every time the showerhead is passing that particular location. On the other hand the methodology quantifies experimentally how much resist profile change and CD-variation is caused by a particular pre- and post-soak time, by testing the process in a virtual immersion set-up and measuring the CD-response with high-precision scatterometry. In this way, we were able to predict CD-variations related to immersion soak. Using the initial resist and topcoat processes, we recently experimentally verified on the ASML XT:1250Di immersion tool at IMEC that these soak related CD-variations exist. The effects are small, but in line with the soak time simulations and the CD-response obtained on the virtual immersion set-up. This demonstrates that the methodology described above could be very useful to select materials for lithography processes and to set specifications for allowed CD-variations in line with to the over-all allowed CD-budget.© (2005) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Increasing design complexity in sub-90nm designs results in increased mask complexity and cost. Resolution enhancement techniques (RET) such as assist feature addition, phase shifting (attenuated PSM) and aggressive optical proximity correction (OPC) help in preserving feature fidelity in silicon but increase mask complexity and cost. Data volume increase with rise in mask complexity is becoming prohibitive for manufacturing. Mask cost is determined by mask write time and mask inspection time, which are directly related to the complexity of features printed on the mask. Aggressive RET increase complexity by adding assist features and by modifying existing features. Passing design intent to OPC has been identified as a solution for reducing mask complexity and cost in several recent works. The goal of <i>design-aware</i> OPC is to relax OPC tolerances of layout features to minimize mask cost, without sacrificing parametric yield. To convey optimal OPC tolerances for manufacturing, design optimization should drive OPC tolerance optimization using models of mask cost for devices and wires. Design optimization should be aware of impact of OPC correction levels on mask cost and performance of the design. This work introduces mask cost characterization (MCC) that quantifies OPC complexity, measured in terms of fracture count of the mask, for different OPC tolerances. MCC with different OPC tolerances is a critical step in linking design and manufacturing. In this paper, we present a MCC methodology that provides models of fracture count of standard cells and wire patterns for use in design optimization. MCC cannot be performed by designers as they do not have access to foundry OPC recipes and RET tools. To build a fracture count model, we perform OPC and fracturing on a limited set of standard cells and wire configurations with all tolerance combinations. Separately, we identify the characteristics of the layout that impact fracture count. Based on the fracture count (FC) data from OPC and mask data preparation runs, we build models of FC as function of OPC tolerances and layout parameters.

In May 2006, the Mask Design, Drawing, and Inspection Technology Research Department (Mask D2I) at the Association of Super-Advanced Electronics Technologies (ASET) launched a 4-year program for reducing mask manufacturing cost and TAT by concurrent optimization of MDP, mask writing, and mask inspection. As one of the tasks being pursued at the Mask Design Data Technology Research Laboratory, we have evaluated the effect of reducing the drawing shot counts by utilizing the repeating patterns, and showed positive impact on mask making by using CP drawing. During the past four years, we have developed a software to extract repeating patterns from fractured OPCed mask data which can be used to minimize the shot counts. In this evaluation, we have used an actual device production data obtained from the member companies of MaskD2I. To the extraction software we added new functions for extracting common repeating patterns from a set of multiple masks, and studied how this step can reduce the counts in comparison to the shot counts required during the conventional mask writing techniques. We have also developed software that uses the extraction result of repeating patterns and prepares drawing-data for the MCC/CP drawing system, which has been developed at the Mask Writing Equipment Technology Research Laboratory. With this software, we have simulated EB proximity effect on CP writing and examined how it affect the shot count reduction where CP shots with large CD errors are to be divided into VSB shots. In this paper, we will report the evaluation result of the practical application of repeating patterns in mask writing with this software.