Advanced data preparation and design automation

The requirements for advanced lithography solutions are constantly increasing. Up to now the optical lithography with its extension into the immersion lithography and strong resolution enhancement techniques (RET) represents the lithography solution of choice. With decreasing critical dimensions (CD) new approaches are needed to provide cost effective methods for small and medium volume production on one side and for efficient photomask fabrication including the RET on the other side. A viable solution for both application fields is the Multi Shaped Beam (MSB) technology, which is currently being developed at Vistec Electron Beam in Jena. E-beam technology has already been used for R&D as well as prototyping applications well ahead of the respective production technology node. It is as well the technology of choice for the future mask fabrication. However, the decreasing CD and thus increasing pattern density asks for new ideas to overcome the throughput challenges faced today. This bottleneck is addressed by parallel writing methods where MSB is one of these techniques. In correlation with the MSB writing technology an appropriate data preparation path is mandatory. One major criterion for the performance of MSB data processing is the shot count reduction which can be reached for different types of patterns. In this paper results from an analysis of the current status of MSB shot segmentation are reported. Beside collecting statistical data of the individual structure size distribution an analysis of the shot count on different pattern coming from mask write as well as direct write applications was carried out. This was performed for different technology nodes and the results are compared.

Increasing design complexity in sub-90nm designs results in increased mask complexity and cost. Resolution enhancement techniques (RET) such as assist feature addition, phase shifting (attenuated PSM) and aggressive optical proximity correction (OPC) help in preserving feature fidelity in silicon but increase mask complexity and cost. Data volume increase with rise in mask complexity is becoming prohibitive for manufacturing. Mask cost is determined by mask write time and mask inspection time, which are directly related to the complexity of features printed on the mask. Aggressive RET increase complexity by adding assist features and by modifying existing features. Passing design intent to OPC has been identified as a solution for reducing mask complexity and cost in several recent works. The goal of <i>design-aware</i> OPC is to relax OPC tolerances of layout features to minimize mask cost, without sacrificing parametric yield. To convey optimal OPC tolerances for manufacturing, design optimization should drive OPC tolerance optimization using models of mask cost for devices and wires. Design optimization should be aware of impact of OPC correction levels on mask cost and performance of the design. This work introduces mask cost characterization (MCC) that quantifies OPC complexity, measured in terms of fracture count of the mask, for different OPC tolerances. MCC with different OPC tolerances is a critical step in linking design and manufacturing. In this paper, we present a MCC methodology that provides models of fracture count of standard cells and wire patterns for use in design optimization. MCC cannot be performed by designers as they do not have access to foundry OPC recipes and RET tools. To build a fracture count model, we perform OPC and fracturing on a limited set of standard cells and wire configurations with all tolerance combinations. Separately, we identify the characteristics of the layout that impact fracture count. Based on the fracture count (FC) data from OPC and mask data preparation runs, we build models of FC as function of OPC tolerances and layout parameters.

The model calibration process, in a resolution enhancement technique (RET) flow, is one of the most critical steps towards building an accurate OPC recipe. RET simulation platforms use models for predicting latent images in the wafer due to exposure of different design layouts. Accurate models can precisely capture the proximity effects for the lithographic process and help RET engineers build the proper recipes to obtain high yield. To calibrate OPC models, test geometries are created and exposed through the lithography environment that we want to model, and metrology data are collected for these geometries. This data is then used to tune or calibrate the model parameters. Metrology tools usually provide critical dimension (CD) data and not edge placement error (EPE - the displacement between the polygon and resist edge) data however model calibration requires EPE data for simulation. To work around this problem, only symmetrical geometries are used since, having this constraint, EPE can be easily extracted from CD measurements. In real designs, it is more likely to encounter asymmetrical structures as well as complex 2D structures that cannot easily be made symmetrical, especially when we talk about technology nodes for 65nm and beyond. The absence of 2D and asymmetric test structures in the calibration process would require models to interpolate or extrapolate the EPE's for these structures in a real design. In this paper we present an approach to extract the EPE information from both SEM images and contours extracted by the metrology tools for structures on test wafers, and directly use them in the calibration of a 55nm poly process. These new EPE structures would now mimic the complexity of real 2D designs. Each of these structures can be individually weighed according to the data variance. Model accuracy is then compared to the conventional method of calibration using symmetrical data only. The paper also illustrates the ability of the new flow to extract more accurate measurement out of wafer data that are more immune to errors compared to the conventional method.

The fast pattern shrinkage of DRAM has driven the lithography technology into the low k1 regime for sub-60 nm technology node. There are a lot of resolution enhancement techniques (RETs) e.g. OPC (Optical Proximity Correction), SB (Scattering Bar), SRAF (Sub-Resolution Assist Features) and DDL (Double Dipole Lithography) and Alternating PSM to enable the low k1 lithography [4]. However, among the RETs, the alternating PSM technique is a high cost solution because double exposure is needed to avoid phase conflict error. Therefore, the implementation of alternating PSM with single exposure for gate conductor layer is the main purpose of this study. Many kinds of pattern and phase designs in the main cell and periphery were investigated.

Resolution Enhancement Techniques (RETs) are critical for meeting the stringent requirements of advanced technology nodes in semiconductor manufacturing. Source Mask Optimization (SMO), a prominent RET methodology, simultaneously co-optimizes photomask patterns and illumination sources to maximize the lithographic process window; nevertheless, existing SMO approaches typically separate source and mask optimization into sequential steps, resulting in substantial computational overhead and lacking convergence guarantees. In this work, we present BiSMO, a unified bilevel optimization framework that formulates SMO as a nested optimization problem and leverages three novel gradient-based algorithms for efficient and provably convergent solution search. To further enhance practical performance, we introduce BiSMO-RL, a reinforcement learning–driven extension that dynamically adjusts bilevel optimization hyperparameters to accelerate convergence and improve solution robustness. Experimental results on representative lithographic patterns demonstrate that BiSMO-RL reduces critical lithographic error metrics by up to 40% and achieves more than an 8× improvement in computational efficiency compared to state-of-the-art RET methods. All code and experimental settings are open-sourced at https://github.com/dekura/BiSMO.git.

Sub-Resolution Assist Feature (SRAF) insertion is one of the most important Resolution Enhancement Techniques (RET) for the 65 nm, 45 nm nodes and beyond. In this paper, we are proposing a novel approach for the optimum placement of SRAF structures using state of the art Calibre RET flow. In this approach, the optimal SRAF shapes are achieved simultaneously during the Optical Proximity Correction (OPC) stage. The main features and the SRAFs are optimized to account for their edge placement and process window metrics respectively. The resulting mask shapes deliver some of the properties that can be obtained using the Inverse Lithography Techniques (ILT), such as excellent Process Window Performance, while there is almost no impact on the runtime. The implemented model-based optimization flow remains compatible with the current OPC production flows.

With the technology node entering 45nm and below and the delay of the EUV lithography, the resolution enhancement techniques (RET) has been considered indispensable to extend the life time of conventional 193nm lithography. Traditional RETs, for example, optical proximity correction (OPC), phase-shifting mask (PSM), inverse lithography technique (ILT) and so on, use a fixed source thus limiting the degrees of freedom during the mask pattern optimization. To overcome the restriction, recently, source and mask co-optimization (SMO) has been proposed as a strong contender in RET. However, SMO is very computationally intensive. To mitigate the issue, we adopt a method which has demonstrated in good effectivity and efficiency in illumination source optimization. Based on the gray-level pixel based source representation, the gradient of the cost function is calculated to guide optimization to improve the wafer image fidelity and depth of focus (DOF). Moreover, the similar method has been used in mask optimization to form a complete SMO algorithm. The SMO algorithm is demonstrated using two mask patterns with critical dimension (CD) of 45nm, including a periodic array of contact holes and a tri-bar pattern. Both the results showed high image quality have been achieved using our SMO algorithm.

The 22nm node will be patterned with very challenging Resolution Enhancement Techniques (RETs) such as double exposure or double patterning. Even with those extreme RETs, the k1 factor is expected to be less than 0.3. There is some concern in the industry that traditional edge-based simulate-then-move Optical Proximity Correction (OPC) may not be up to the challenges expected at the 22nm node. Previous work presented the advantages of a so-called inverse OPC approach when coupled with extreme RETs or illumination schemes. The smooth mask contours resulting from inverse corrections were shown not to be limited by topological identity, feedback locality, or fragment conformity. In short, inverse OPC can produce practically unconstrained and often non-intuitive mask shapes. The authors will expand this comparison between traditional and inverse OPC to include likely 22nm RETs such as double dipole lithography and double patterning, comparing dimensional control through process window for each OPC method. The impact of mask simplification of the inverse OPC shapes into shapes which can be reliably manufactured will also be explored.

Today's design flows sign-off performance and power prior to application of resolution enhancement techniques (RETs). Together with process variations, RETs can lead to substantial difference between post-layout and on-silicon performance and power. Lithography simulation enables estimation of on-silicon feature sizes at different process conditions. However, current lithography simulation tools are completely shape-based and not connected to the design in any way. This prevents designers from estimating on-silicon performance and power and consequently most chips are designed for pessimistic worst-cases. In this paper we present a novel methodology that uses the result of lithography simulation for estimation of performance and power of a design using standard device- and chip-level analysis tools. The key challenge addressed by our methodology is to transform shapes generated by lithography simulation to a form that is acceptable by standard analysis tools such that electrical properties are preserved. Our approach is sufficiently fast to be run full-chip on all layers of a large design. We observe that while the difference in power and performance estimates at post-layout and on-silicon is small at ideal process conditions, it increases substantially at non-ideal process conditions. With our RET recipes, linewidths tend to decrease with defocus for most patterns. According to the proposed analyses of layouts litho-simulated at 100nm defocus, leakage increases by up to 68%, setup time improves by up to 14%, and dynamic power reduces by up to 2%. The key challenge addressed by our methodology is to transform shapes generated by lithography simulation to a form that is acceptable by standard analysis tools such that electrical properties are preserved. Our approach is sufficiently fast to be run full-chip on all layers of a large design. We observe that while the difference in power and performance estimates at post-layout and on-silicon is small at ideal process conditions, it increases substantially at non-ideal process conditions. With our RET recipes, linewidths tend to decrease with defocus for most patterns. According to the proposed analyses of layouts litho-simulated at 100nm defocus, leakage increases by up to 68%, setup time improves by up to 14%, and dynamic power reduces by up to 2%.

The feasibility of Hot Spot Fixing (HSF) system in DfM flow is studied and reported. Hot spot fixing using process simulation is indispensable under low-k1 lithography process for logic devices with advanced design rule (DR). Hot spot such as pinching, bridging, line-end shortening will occur, mainly depending on local pattern context. Proper calibration of DR, mask data preparation (MDP), resolution enhancement technique (RET) and optical proximity effect correction (OPC) will reduce potential hot spots. However, pattern layout variety is so enormous that, even with most careful calibration of every process, unexpected potential hot spots are occasionally left in the design layout 1-2. OPC optimization is useful for maximizing common process margin, but it cannot expand individual pattern's process margin without modification of design layout. So, at an early design stage, hot spot extraction using lithography compliance check (LCC) and manual modification of design at hot spots will be a simple and useful method. The problem is that, it is difficult to determine how to modify layout in order to be consistent with DR, MDP/OPC rule. For proper layout modification, intimate knowledge of the entire process would be necessary, and moreover, the modification work often tends to be iterative, and thus time-consuming. Therefore, using our automated HSF system in the cell design stage and also the chip design stage is helpful for fixing design layout while avoiding fatal hot spot occurrence, with enough process margin and also with short turnaround time (TAT) 3-4. The basic system flow in the developed system is as follows; LCC extracts potential hot spots, and the hot spots are categorized by lithography error mode, grade, and surrounding context. And then, hot spot modification instructor, taking the surrounding situation into consideration, generates modification guide for every hot spot. Design data is automatically modified according to the instruction at every hot spot, complying with the design rule. The design modification process is verified with design-rule checker (DRC) and process simulation to confirm hot spot elimination without side effect. In this work, HSF is implemented in the design flow for various logic devices of 65 nm node. We extend modification target layers to multiple critical layers, including active area, poly, local metal wire and intermediate metal wire. The feasibility of the provided HSF system has been studied by applying it to around one hundred data of various sizes with respect to pattern fixing rate and turn around time (TAT). Moreover, process margin expansion including depth of focus (DOF) and exposure latitude (EL), in small layout was verified using process simulation and also by experimental results, namely, scanning electron microscope (SEM) images of focus exposure matrix. The detailed results are shown in the paper.

Reticle cost and cycle time to deliver new circuit design s to a wafer fab remain key focus areas for advanced semiconductor manufacturing and new product development. Resolution enhancement techniques like optical proximity correction as applied to critical layers ha ve increased the burden on mask data pr eparation and reticle writing steps of the mask making flow. The growing data volume and complexity of designs must be reduced to a perfect image on a reticle in the shortest time possible against computer and machine constraints. Continued dependence on 193 nm wavelength exposure in extremely low k 1 lithography exacerbates the underlying trends. Two important factors come together to drive the economics and performance of the reticle line: the complexity of the designs and the productivity of e-beam writing tools. The designs, OPC methods , and writing tool capabilities continue to evolve with each node of technology. The study builds on prior evaluations to look at fundamental pattern complexity across 90nm, 65nm, and 45nm logic designs using the gate and metal-1 critical layers. The writing tool throughput testing uses a range of standard patterns to establish shot limited performance as a calibration method for arbitrary designs. Node to node design and tool to tool generation comparisons highlight actual step changes in complexity and capability by introducing new quantitative methods, be nchmarking metrics, and testing strategi es. The findings are projected into the future using design complexity and writing tool trends to suggest implications about reticle cost, cycle time, or possible gaps in technology development. Keywords : mask data volume, pattern file size, RET, OPC, write time, data density, geometric content

Nanometer VLSI design is greatly challenged by the lithography limitations. Existing approaches in design for manufacturability (DFM) are mostly done post design, such as mask data preparation using various resolution enhancement techniques (RETs), rather than during design. To really bridge the gap between design and manufacturing, it is important to model and feed proper lithography metrics upstream to guide the proactive lithography aware physical design (LAPD). In this paper, we will discuss some key aspects of LAPD

With the resolution enhancement techniques such as OPC (Optical Proximity Correction) and SRAF (Sub-Resolution Assist Features), the size of layout data have grown significantly. It is quite common now to find layout files that are tens of GBs in size. Unlike GDSII which can store data hierarchically, mask data formats such as MEBES are essentially flat and more voluminous. Moreover, polygonal data present in layout data files is fractured, thereby increasing the data volume before getting stored in MEBES data format. This results in huge MEBES files. As per the ITRS roadmap of 2005, for a 45nm half-pitch node that is expected to be in use by 2010, the mask data volume for a single layer is expected to reach up to 825 GB. Storing and transferring such large mask data are issues for which the mask industry needs solutions. Historically, MEBES is the most prevalent EB format in the industry. Moreover, in many Mask Data Preparation (MDP) flows, the MEBES format is being used as the de-facto standard for specifying the fractured EB data even though the final target EB machine might be different. In this paper we present techniques for lossless reversible compression of MEBES data, i.e., when the compressed file is decompressed, the generated uncompressed file matches the original MEBES file bit- by-bit. By applying these compression techniques a compression ratio of 5X to 15X can be obtained. In practice, compressing MEBES files is usually a one-time task, but decompression of compressed files is expected to be done multiple times as every time a compressed MEBES file needs processing, it has to be decompressed. MEBES is essentially an efficient data format and the geometries are stored compactly. As a result the compression/decompression techniques described in this paper are quite computation intensive in order to achieve higher compression ratio. This in turn leads to higher CPU time for compression/decompression compared to generic compressors such as gzip. However, as the format-specific compressors produce higher compression ratios, the disk I/O time for compression and decompression is expected to be less compared to the generic compressors such as gzip and gunzip. In spite of this, the format-specific decompressor is usually 3-5X times slower than the generic decompressor such as gunzip. Since decompression is expected to be done more frequently as compared to compression, speeding up decompression is highly desirable. We present a compression technique for MEBES data which enables multiple process threads to decompress the compressed MEBES data. With the multi-core multiprocessor machines becoming quite inexpensive and common, the multi-threaded decompression is expected to perform close to the disk I/O time on such machines. The paper details out the techniques, experimental results in terms of comparative compression ratios, compression and decompression speed using single threads and multiple threads. The possibility of getting higher compression ratios as well as higher or comparable decompression speed makes it more practical to use format specific reversible compression schemes rather than using generic compressors. Even though, the paper focuses on compression and decompression of MEBES, it can be easily extended to the compression of GDSII [1].

Traditionally, an IC became ready for fabrication after an IC design was converted into a physical layout, the timing veried, and the polygons certied to be DRC-clean. e data les representing the various layers were shipped to a mask shop, which used mask-writing equipment to convert each data layer into a corresponding mask, and the masks were then shipped to the fab where they were used to repeatedly manufacture the designs in silicon.

Although techniques for resolution enhancement in single-aspect radar imaging have made rapid progress in recent years, it does not necessarily imply that such enhanced images will improve target identification or recognition. However, when multiple looks of the same target from different aspects are obtained, the available knowledge base increases allowing more useful target information to be extracted. Physics based image fusion techniques can be developed by processing the raw data collected from multiple ISAR sensors, even if these individual images are at different resolutions. We derive an appropriate data fusion rule in order to generate a composite image containing increased target shape characteristics for improved target recognition. The rule maps multiple data sets collected by multiple radars with different system parameters on to the same spatial-frequency space. The composite image can be reconstructed using the inverse 2-D Fourier transform over the separated multiple integration areas. An algorithm called the matrix Fourier transform is created to realize such a complicated integral. This algorithm can be regarded as an exact interpolation, such that there is no information loss caused by data fusion. The rotation centers need to be carefully selected in order to properly register the multiple images before performing the fusion. A comparison of the IAR (Image Attribute Rating) curve between the fused image and the spatial-averaged images quantifies the improvement in the detected target features. The technique shows considerable improvement over a simple spatial averaging algorithm and thereby enhances target recognition.