Simplified and Generalized BV-VTEAM Model for Bipolar Memristors and Its Application in Digital Logic Circuit Design

Directed acyclic graphs (DAGs) are useful for modeling of quantum-dot cellular automata (QCA)-based digital circuits. In this paper, DAGs are used to design the single-layer architecture of QCA circuits. A context-free grammar is proposed to check whether a majority gate-based Boolean expression is syntactically correct or not. Whether a given sentence satisfies the grammar can be tested using the corresponding parse tree. Language-independent (three-address) code can then be constructed from the parse tree to draw a DAG and thereby design the QCA circuit corresponding to a given Boolean expression. The clock zones are partitioned according to each level of the DAG. The abstract architecture developed from the DAG is simulated using the QCADesigner tool.

The Quine-McCluskey method is an algorithm to minimize Boolean functions. Although the method can be programmed on computers, it takes a long time to return the set of prime implicants, thus slowing the analysis and design of digital logic circuits. As a result, it slows down the dynamic reconfiguration process of programmable logic devices. In this paper, we first propose a data representation for storing implicants in memory to reduce the cache misses of the program. We then propose an algorithm to find all prime implicants of a Boolean function. The algorithm aims to reuse the data available on cache, thus decreasing cache misses. After that, we propose an algorithm for step 2 of the Quine-McCluskey method to select the minimal number of essential prime implicants. The evaluation shows that our proposals achieve much higher performance than the original Quine-McCluskey method. The number of essential prime implicants is a low percentage, less than 50%, of the total prime implicants generated in step 1 of the method.

This paper primarily focuses on Gate Diffusion Input (GDI) technique used for the implementation of digital logic circuits. It also discusses in detail the limitations and modifications of the basic GDI technique. Initially, GDI was a new technique used for low power digital combinational circuit design. This approach provides a reduction in power consumption, propagation delay, and area of digital circuits while the logic design complexity is small. GDI methodology allows implementation of a wide range of complex logic functions using only two transistors. GDI is a new technique for digital circuits implementation with a lot of advantages over existing ones. This paper also analyzes the recent applications of GDI technique which are the implementation of MASH 1-1 and MOD 2 modulator for Sigma Delta DACs and development of full adders for efficient arithmetic operations.

The low carrier mobility of (printed) semiconductors and high variations of the printed/flexible electronic elements are some of the most difficult challenges for the practical realization of complex printed/flexible electronic circuits. Although contemporary circuit designs accommodate some degree of process variations in conventional silicon processes largely by negative feedback, negative feedback is largely inapplicable in printed/flexible electronics. This is because the gain of the transistors is too low in electronic circuits to realize high open-loop gain, but also because negative feedback is inapplicable to digital circuits in the traditional sense. In this paper, we describe the co-design between the first three supply chains of Printed/Flexible Electronics – the co-design between our modified semiconductor, Fully-Additive Low-Temperature All-Air Low-Variation Printed/Flexible Electronics printing process and a process-variation-tolerant digital circuit design methodology. The first two co-design supply chains pertain to a low-cost screen-printing process while the last co-design chain pertains to the Quasi-Delay-Insensitive asynchronous-logic digital design methodology (vis-a-vis synchronous-logic) that is self-timed, hence virtually tolerant to any variations. We will also delineate our measurements on digital circuit based on codesign of the aforesaid supply chains, depicting the merits of our modified semiconductor, low-variation printing process, and the ensuing functional printed digital circuit.

In this paper, the authors present a rapid prototyping environment for teaching digital logic design. Their primary goal was to build an FPGA based hardware prototyping system that provides sufficient flexibility for the implementation and functional verification of various digital circuit designs. Since the system is intended to be used as an experimental and demonstration board to support digital design courses and practices for the undergraduate students, it is simple to use and completely supported by the software for automatic implementation of digital circuits. The prototyping environment consists of a PC and the programmable board composed of 3 FPGAs. One FPGA is used to implement the digital circuit, while the rest of the devices implement an interface between the digital circuit and the PC. The PC is used for designing a digital circuit, automatic generation of the interface logic, programming the FPGAs and as a test engine for functional verification of the designed circuit. The presented environment is used in the regular educational process and the sample student projects are summarized.

Compact low-power devices with ultrafast processing speed are the fundamental building blocks for the development of the state-of-the-art logic systems and memristor prominently fulfills these demands and plays a major role in digital circuit design. In this work, design, implementation, and performance evaluation of memristor-based logic gates, such as NOT, AND, NAND, OR, NOR, XOR, and XNOR, and combinational logic circuits, such as adder, subtractor, and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2\times1$ </tex-math></inline-formula> mux, are presented via SPECTRE in Cadence Virtuoso. Herein, we propose an optimized design of memristor-based logic gates and combinational logic circuits and draw a comparative analysis with the conventional 180-nm complementary metal–oxide–semiconductor (CMOS) technology. The utilized memristor model is thoroughly validated with the experimental results of a high-density <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{Y}_{{2}}\text{O}_{{3}}$ </tex-math></inline-formula> -based memristive crossbar array (MCA), which shows a significantly low values of coefficient of variabilities in device-to-device (D2D) and cycle-to-cycle (C2C) operation. The area, power, and delay calculated from these combinational circuits are found to be reduced by more than 71.4%, 40%, and 54%, respectively, as compared to the conventional 180-nm CMOS technology. The impact of multiple CMOS technology nodes (90 and 180 nm) on the power consumption at the chip-level logic circuit implementation has also been investigated. The adopted memristor-based design significantly improves the performance of various logic designs, which makes it area and power efficient and enables a major breakthrough in designing various low-power, low-cost, ultrafast, and compact circuits.

This paper presents a fully digital implementation of a memristor hardware (HW) simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field-programmable gate array families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks, implementing examples of associative memory and unsupervised learning of spatiotemporal correlations in parallel input streams using a simplified spike-timing-dependent plasticity. We provide the full circuit schematics of all our digital circuit designs and comment on the required HW resources and their scaling trends, thus presenting a design framework for applications based on our HW simulator.

Digital integrated circuit design serves as a crucial required course for students majoring in electronic science and technology. This subject combines theoretical knowledge with practical applications, playing a key role in establishing a strong foundation for students’ academic and career growth. Guided by the OBE concept, the reform of digital integrated circuit design aims to transcend traditional limitations, explore more efficient and high-quality teaching methods, and cultivate outstanding talents according to predefined goals, enabling them to meet job market demands and adapt to industry changes. To enhance the training model for professional talents in electronic science and technology and support the long-term development and planning of students, this approach achieves multiple objectives simultaneously. Consequently, this paper explores the essence of the OBE concept and provides an in-depth analysis of the current state and potential reform directions for the digital integrated circuit design course, aiming to offer valuable insights for educators on the front lines.

In this paper, a behavioral SPICE memristor model for digital logic implementation is presented and demonstrated in LTSpice. We show binarized state switching and voltage thresholding in the model, which are both important features in practical digital systems. The use of this SPICE model is straightforward and intuitive because almost all parameters in the model can be changed according to the application, including the threshold voltage and the memristance. The LTSpice circuit simulation shows the same characteristics as the original MATLAB numerical implementation, which means that the circuit-level SPICE model can be integrated with other designs. Three types of memristor digital logic circuits are simulated with the LTSpice model with positive results, which proves that the behavioral memristor model has potential application in digital system design.

Electronic Design Automation (EDA) technology represents the development direction of modern electronic design technology. This paper presents the traditional digital circuit design method, carefully introduces a top-down hierarchy design method, analyzes advantages and disadvantages of traditional experimental teaching, and proposes the application of EDA experimentation in digital circuit design. It is comprised of hardware and software. Numerical Control Frequency divider is taken as a typical example to display EDA experimental applications. An EDA experimental system based on FPGA/CPLD can achieve automated design of digital circuit quickly and easily, and thus it provides a good platform for the logic design and development of medium and large-scale digital circuit.

The article presents and describes in detail the laboratory work “Digital circuit design and algebra of logic: creation of digital devices in an online simulator”, conducted for high school students at Bauman Moscow State Technical University. The introduction describes the place of the lesson in the system of interaction between organizations of secondary general and higher levels of education; based on the considered problems of education in the field of digital circuitry, the rationale for the need for this laboratory work is given. The practice-oriented nature of the considered laboratory work in informatics necessitates the use of modern modeling tools. This laboratory work uses the online environment Logic.ly, which allows you to create and explore digital devices: half-adder, adder, flip-flops, multi-plexers, decoders. The main characteristics, structure and stages of the lesson, subject content and interdisciplinary connections, target subject and meta-subject results based on a modern competency-based approach are described in detail.

This article describes a brief history of the development of the CAD system for integrated circuit design in Russia. The background of the beginning of the import-independent Russian CAD for digital integrated circuit design "Obsidian" is presented. What tasks were set for the developers and which results have been achieved up to the present. The results of a large set of tests obtained by "Obsidian" to compare this system with commercial CAD tools for digital integrated circuit design are presented. Further directions of the development of CAD of digital integrated circuits have been determined for separate stages of the design route.

A new remote laboratory system for learning hardware design and experiment of digital circuit has been developed. It employs shared resources and an e-learning system based on the top-down method specializing in the logic circuit design and featuring a quick acquisition of the hardware-description-language-based design skill. The wide use of the Internet motivated us to develop seamless remote and actual hardware laboratories for hardware design laboratory course, and for students to learn the digital circuit design by themselves. The proposed remote laboratory utilizes actual hardware and actual measurement tools in a time-sharing fashion. The combinatorial use of FPGA/PC connected test hardware and PC-based measurement equipments has made it possible to develop a remote multi-user and time-sharing hardware experiment system. As all students are equipped with high-performance Laptop PCs, CPU intensive development tasks can be performed by each student's client PC in a rich-client environment. The prototype the remote-laboratory and self e-learning system are under-construction, and will be used for the third grade CS students from year 2005

A digital VLSI circuit design for an adaptive resonance theory (ART) neural network architecture, called the augmented ART-1 neural network (AARTI-NN) is presented. An ‘axon-synapse-tree’ structure is used to realize the activities of the short-term memories and reset subsystem. The long-term memory traces are implemented using NMOS transmission gales. PSpice circuit simulation was carried out to verify the design of a prototype, seven-node AARTI-NN. A clock-controlled delay element is included in the simulation to illustrate the functionality of the AARTI-NN. It is shown that the AARTI-NN node selection activities simulated from the circuit designed are identical to those described by the coupled differential equations governing the AARTI-NN.

Advancements in Silicon Carbide (SiC) digital integrated circuit (IC) design have enabled the ability to design complex, dense, digital blocks. Because of the large number of transistors, these complex digital designs make the time and risk of hand-crafted digital design, which has been the norm for SiC, too costly and risky. For large scale integrated digital circuits, computer aided design (CAD) tools are necessary, specifically the use of automatic synthesis, rule-based placement and signal routing software. The tools are used in progression as a design flow and are necessary for the timely and accurate creation of high-density digital designs. Application of an automated digital design flow to high-temperature SiC processes presents new challenges, such as extraction of timing characteristics at high temperatures, specifically above 400°C, as well as managing the complexity of synthesis, optimization of cell placement, verification of timing enclosure, and identifying routing constraints. These activities all require a willingness to extend and enhance the CAD software. Presented is a high temperature SiC digital synthesis flow. This flow is fully integrated with the characterization of a standard cell library that considers the variation of voltage, temperature, and process characteristics. A digital controller for a 10,000-pixel UV focal plan array (FPA) in a SiC CMOS process was designed using this high temperature digital flow. The controller is comprised of a finite state machine (FSM), that monitors several counters, shift registers and combinational logic feedback signals. The FSM is configured to optimize the FPA for different applications and exposures. The Register-Transfer Level (RTL) design of the FSM produces between 900 and 1,000 gates, depending on the temperature-dependent time closure with a total footprint of 14mm2. Typical SiC processes present a non-monotonic clock speed over temperature. The advantage of this digital design flow is that it allows the designer to target a temperature corner for the netlist design but verify its operation over a &amp;gt; 400°C operating range. This flow is currently being enhanced for use with NASA's SiC JFET-R process to create a high temperature communication protocol interface.