Simultaneous Conversions with the Residue Number System Using Linear Algebra

Elliptic Curve Cryptography operations rely heavily on the strong security of scalar multiplication. However, this operation is vulnerable to side channel (SCA) and fault injection (FA) attacks. The use of alternative arithmetic systems like Residue Number System (RNS) for all scalar multiplication underline operations has been proposed as an efficient countermeasure approach for the above attacks. In RNS, a number is represented as a set of smaller numbers, where each one is the result of the modular reduction with a given moduli basis. Under certain requirements, a number can be uniquely transformed from the integers to the RNS domain (and vice versa) and all arithmetic operations can be performed in RNS. This representation provides an inherent SCA and FA resistance to many attacks and can be further enhanced by additional RNS arithmetic manipulations or more traditional algorithmic countermeasures. In this paper, extending our previous work, we explore the potentials of RNS as an SCA and FA countermeasure. A description of RNS based SCA and FA resistance means is provided through appropriate scalar multiplication algorithmic variations, traces of the proposed algorithm are collected and the results are analyzed regarding the RNS countermeasure strength. More specifically, in this paper, a secure RNS based Montgomery Power Ladder based scalar multiplication algorithm is provided and is implemented on an ARM Cortex A7 processor. The implementation SCA-FA resistance is evaluated by collecting preliminary leakage trace results that validate our initial assumptions.

This paper describes a new scheme for matrix multiplication in the residue number system (RNS) by a VLSI systolic structure. The basic goal is to accelerate matrix multiplication by exploiting the double parallelism involved in the systolic structure and in the RNS. The scheme consists of a N × N rhombus-like array of residue-based processors for RNS N × N matrix multiplication. Each processor operates in parallel, pipeline or hybrid modes using an arrangement of q moduli adders and multipliers, q>1. The operations of residue addition and multiplication are performed by associative table lookup processing, which has been shown to be particularly efficient for fast residue arithmetic implementations in VLSI technology.

In order to get an efficient comprehensive analysis on Doppler estimation in RADAR; need an enhanced arithmetic formulation procedure for density, power and latency optimisations. Modular adders and multipliers are very crucial components in the performance of residue number system-based applications. The Residue Number System (RNS) is a non-positional number system that allows parallel computations without transfers between digits. However, some operations in RNS require knowledge of the positional characteristic of a number. Among these operations is the conversion from RNS to the positional number system. The methods of reverse conversion for general form moduli based on the Chinese remainder theorem and the mixed-radix conversion are considered, as well as the optimized methods for special form moduli. A modified New CRT-I & New CRT-II with conjugate moduli set is considered to implement adder, multipliers and subtractions with optimised algorithms. This paper mainly deals with the conversion of numbers from binary to RNS as well RNS to binary with the specific modulo {2^n±k} which proves this new method. Modified Radix16 booth encoding algorithm and square carry bypass adder are used in implementation of RNS system to reduce parameter constraints.

Abstract—A new residue number system algebra has been previously proposed by the author. The algebra has solved an essential theoretical barrier in the residue number system and has enabled one to pursue additive operations in the residue number system to their full extent, overcoming such difficulties as restrictions on the sign or magnitude of numbers in the system. In this paper, basic theorems in the algebra are introduced first, and then, based on the theorems, table look-up oriented solutions for hardware overflow checking, sign detection, and floating-point additive operations are given. The theorems expound the behavior of a quantity treated as a veiled mysterious function in the literature. To the best knowledge of the author, hardware overflow-checking schemes and floatingpoint additive operations in the residue number system have never been reported elsewhere. So far, the upper limit of the magnitude of numbers in the system ever discussed has been the one that is theory-limited, and floating-point operations in the residue number system have never been discussed.

An elliptic curve point multiplier (ECPM) is the main part of all elliptic curve cryptography (ECC) systems and its performance is decisive for the performance of the overall cryptosystem. A VLSI residue number system (RNS) architecture of an ECPM is presented in this paper. In the proposed approach, the necessary mathematical conditions that need to be satisfied, in order to replace typical finite field circuits with RNS ones, are investigated. It is shown that such an application is feasible and that it leads to a significant improvement in the execution time of a scalar point multiplication.

The paper presents algorithms for the generation of Residue Number System (RNS) triples with $SQ=2^{k}-1$ and quadruples with $SQ=2^{k}$ for some k. Triples and quadruples allow us to design efficient hardware implementations of non-modular operations in RNS such as division, sign detection, comparison of numbers, reverse conversion with using of a diagonal function from requiring division with the remainder by the diagonal module SQ. Division with a remainder in the general case is the most complex arithmetic operation in computer technology. However, the consideration of special cases can significantly simplify this operation and increase the efficiency of hardware implementation. We show that there are 5573 good RNS triples (2301 even and 2372 odd) with elements less than 10 000, as the values of SQ vary from $2^{5}-1$ to $2^{27}-1$ . In contrast, RNS quadruples with $SQ=2^{k}$ seem to be quite rare. Restricting our search to sums of the elements in a quadruple less than 4000 we find that exactly 31 such quadruples exist. Their values of SQ vary between 220 and 230 with always even exponent. We suggest the measure of RNS balance and find perfectly balanced RNS among triples according to this measure. We demonstrate the advantages of more balanced quadruples by means of hardware implementation.

The scaling operation, i.e. the division by a constant factor followed by rounding, is a commonly used technique for reducing the dynamic range in digital signal processing (DSP) systems. Usually, the constant is a power of two, and the implementation of the scaling is reduced to a right shift. This basic operation is not easily implementable in the residue number system (RNS) due to its non positional nature. A number of different algorithms have been presented in the literature for the RNS scaling. In this paper, several RNS dynamic reduction techniques have been analyzed and the selected one is applied to a polyphase filter bank. A comparison of the filter bank scaled with RNS to binary and binary to RNS conversions, and the RNS scaled implementation is presented. A reduction of area and power consumption of about 30% for the scaling block is obtained.

In this work, we present the implementation of a finite impulse response (FIR) filter in the residue number system (RNS), in which we use a carry-save scheme in the binary representation of the residues to speed-up modular additions. We compare the carry-save RNS implementation with the implementations of the same filter in the traditional binary system and in plain RNS. Results show that the carry-save RNS filter is much faster and its energy dissipation per cycle comparable. Furthermore, we show that a multiple supply voltage approach for the plain RNS filter can lead to an additional reduction in power dissipation without performance degradation.

Wideband chaotic carrier is a promising solution for wideband communication, since it overcomes the disadvantages of both narrowband and spread-spectrum communication. It is particularly suited to realize information encryption for secure communication. Chaotic signals can be generated by using discrete-time non-linear dynamical circuits, since they can exhibit a quasi-chaotic (QC) behavior. A particular implementation of QC digital filters can be based on finite precision arithmetic and, in particular, on residue number system (RNS) circuits, which possess very attractive features with regard to their VLSI implementation. In the present paper, we propose an RNS architecture that can be used in connection with secure communication. Each RNS channel consists of a QC oscillator, having its coefficients belonging to a Galois field defined by a prime modulus. In particular, the QC behavior is ensured by well-known properties of primitive polynomials in this field, which generate the characteristic feedback of the oscillator. We demonstrate in the paper that the proposed RNS architecture yields a cost-effective VLSI implementation, which favorably compares with respect to other secure communication approaches proposed in the technical literature. We obtain encouraging results both in terms of confidentiality of the encrypted information and of throughput rate for real-time applications. Moreover, we propose an extended architecture suited to the protection of the secure communication system against transmission errors, by using the self-correcting ability of Redundant RNS (RRNS).

Computer networks by providing data exchange capability between connected systems are driving a revolution in digital world. However, by improving the technology and producing low price devices, the number of connected devices is rapidly growing, and users are moving from one computer per person to multidevices per person including cell phones, home appliances, and wearable gadgets which are all connected to the internet. Therefore, new network concepts and also challenges have been introducing to overcome issues of rapid growth of the number of connected devices. Moreover, for future network with huge number of members more complex processors are needed to perform required process. Therefore, researchers of these fields should look for novel methods to overcome distinct emerging challenges. Recently, residue number system (RNS) as an alternative method to reduce network operations overhead attracts network researchers. The RNS has been used as a tool to reduce transmission energy and increase reliability in wireless sensor networks. Moreover, RNS can enhance switching process, and substitute lookup tables with simple modular operations in software-defined network. This chapter presents different types of RNS applications in computer networks in order to familiar researchers with these concepts.

Fast RNS (residue number system) algorithms which use only binary arithmetic are developed. Scaled residues, called pseudoresidues, are introduced by exploiting the cycle properties of each RNS channel and solving a Diophantine equation. Using the pseudoresidues instead of the original residue set to perform the desired computations, an RNS processor can be built with standard binary devices of small wordlength. The effectiveness of the procedure is shown by developing the pseudoresidue implementations of a modular multiplier for odd moduli RNS and of a FIR (finite impulse response) filter. The resulting structures exhibit complete reprogrammability for both moduli and coefficients, a very low number of fast machine cycles, and a square time-area product reduction. >

Residue number system (RNS) representations that contain redundant moduli have been extensively studied with regard to their error checking properties. A second form of redundancy in RNS, that of redundant residues, has been applied in certain application contexts to gain speed and cost benefits. Such applications are developed in an ad hoc manner and there does not exist a theoretical framework for the latter variety of redundant RNS. We develop a theory of RNS representations with redundant residues and show how representation parameters affect the speed and complexity of various arithmetic operations. The theory parallels that of redundant signed-digit representations in that at issue are choice of 'residue sets' (akin to digit sets), encoding of residue sets, conversions between residue sets with different degrees of redundancy, including none, and algorithms for arithmetic on redundant-residue operands.

Fully Homomorphic Encryption (FHE) permits processing information in the form of ciphertexts without decryption. It can ensure the security of information in common technologies used today, such as cloud computing, the Internet of Things, and machine learning, among others. A primary disadvantage for its practical application is the low efficiency of sign and comparison operations. Several FHE schemes use the Residue Number System (RNS) to decrease the time complexity of these operations. Converting from the RNS to the positional number system and calculating the positional characteristic of a number are standard approaches for both operations in the RNS domain. In this paper, we propose a new method for comparing numbers and determining the sign of a number in RNS. We focus on the even ranges that are computationally simple due to their peculiarities. We compare the performance of several state-of-art algorithms based on an implementation in C++ and relatively simple moduli with a bit depth from 24 to 64 bits. The experimental analysis shows a better performance of our approach for all the test cases; it improves the sign detection between 1.93 and 15.3 times and the number comparison within 1.55–11.35 times with respect to all the methods and configurations.

Algorithms are developed to compute the number of active devices for residue number system (RNS) and binary number system (BNS) signal processing architectures. The precharged CMOS technology is used in order to build the filter architecture. The ROM lookup table and two's complement multiplier are used as the computational cells in the RNS and BNS, respectively. A direct implementation transversal systolic filter architecture is considered in RNS and BNS algorithms.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The residue number system (RNS) allows high accuracy integer-valued arithmetic operations to be decomposed into independent (carry-free), low accuracy computations that can be performed in parallel. The RNS thus provides an attractive alternative to weighted number systems (e.g., binary or decimal) for high speed numerical computing1. The residue number representation is completely specified by a set of relatively prime moduli. The overall dynamic range is given by the product fo the moduli. Although this dynamic range can be arbitrarily high, the dynamic range required in any individual subcalculation is commensurate only with the associated modulus. The RNS also leads to a reduction in the growth of the total number of combinatorial logic elements required to perform a calculation via truth table approach. Specifically, the RNS exhibits additive growth in spatial complexity with input word size, contrasted by multiplicative (exponential) growth for weighted number systems.