Some polynomially solvable subcases of the detailed routing problem in VLSI design

We consider the Minimum Elmore Delay Steiner Tree Problem, which is a key problem in VLSI design: We are given a set of pins which have to be connected by a Steiner tree. One of the pins is the source. Challenging timing constraints impose tight bounds on the delay of propagating a signal from the source to the other pins. The commonly used measure is Elmore delay (Elmore in J Appl Phys 19:55---63, 1948). We consider two variants: minimizing the maximum Elmore delay or a weighted sum of Elmore delays. Both variants are strongly NP-hard even for very restricted special cases. Although it is a central problem in VLSI design (Kahng and Robins in On optimal interconnections for VLSI. Kluwer, Boston, 1995; Korte and Vygen in Building bridges--between mathematics and computer science. Springer, Berlin, pp 333---368, 2008), no approximation algorithms were known so far. In this work, we give the first constant-factor approximation algorithm. It works for both variants. The algorithm achieves an approximation ratio of 3.39 in the rectilinear plane and 4.11 in general metric spaces. We can show that our algorithm is best possible in a certain sense. We also demonstrate that our algorithm leads to improvements on real world VLSI instances compared to the currently used standard method of computing short Steiner trees.

A hundred fold performance improvement of a CAD tool can bring about a similar increase in design size. Hardware accelerators for CAD tools offer such performance improvements, but are application specific. Though some accelerators can be programmed to adapt themselves to somewhat different applications, it takes as much time and money to reconfigure one as it does to purchase a new one. Hence the use and acceptance of hardware accelerators has been limited. To alleviate the above mentioned problem we demonstrate that a wide variety of problems in VLSI design, viz gate array placement, standard cell placement, PLA folding, channel routing can be mapped on to a single mother problem. From the solution to the mother problem, the solutions to the other problems can be deduced. Therefore, a single hardware accelerator to solve the afore mentioned mother problem along with a translator-deducer kernel to translate the various problems to the mother problem and again decipher the solution would be sufficient to ...

Distributed Genetic Algorithms (DGAs) designed for the Internet have to take its high communication cost into consideration. For island model GAs, the migration topology has a major impact on DGA performance. This paper describes and evaluates an adaptive migration topology optimizer that keeps the communication load low while maintaining high solution quality. Experiments on benchmark problems show that the optimized topology outperforms static or random topologies of the same degree of connectivity. The applicability of the method on real-world problems is demonstrated on a hard optimization problem in VLSI design.

Timing optimization is one of the most significant problems in VLSI design because it determines performance of the designed circuit. Such optimization problems contain hundreds of thousands of variables therefore they may be classified as high performance computing problems. In this paper we present the results of our parallel implementation of two popular approaches to integrated circuit timing optimization. Both approaches are based on the analytical placement computational scheme. The first approach is iterative net-weighting placement. The second executes buffer insertion algorithm after the placement cycle. We analyze effectiveness of both approaches, discuss their drawbacks and suggest ways of improvement.KeywordsVLSI CADtiming-driven designphysical design algorithmsplacementbufferingstatic timing analysismulticore architecture

Energy optimization for high-capacitance on-chip buses has become a critical problem in VLSI design, especially for embedded or SoC systems. Coupling effects between bus wires make this issue even more urgent. Coding schemes have been proposed to reduce the energy dissipation. However, the circuits overhead increases significantly when the coding schemes consider the inter-wire capacitances. In this paper, we present a novel method for energy optimization in memory address bus (MAB). The data on application specified MAB has different characters to the data bus, which has high repetition vectors and unevenly distributed switch activity. Thus a combined method is proposed to optimize the energy consumption by both self capacitance and inter-wire capacitance. First, we lower the switch activity by an efficient coding scheme. Based on the statistical data, a modified bus-invert coding scheme can intelligently divide bus lines into groups and apply bus-invert coding. It brings ultra-low area or timing penalty because of the simple circuit structure. Then the energy consumption of coupling capacitances is optimized by net reordering technique. Implemented with table-look-up technique, a fast simulated annealing algorithm is proposed to solve the net reordering problem. The experimental results show that our combined method is very efficient to reduce the energy consumption in memory address bus for varieties of applications.

Two major problems are involved in VLSI design, namely, the placement of components and routing between these components. Single row routing problem is a combinatorial optimization problem of significant importance for the design of complex VLSI multi layer printed circuit boards (PCB's). The design involves conductor routing that makes all the necessary wiring and interconnections between the PCB modules, such as pins, vias, and backplanes. In very large systems, the number of interconnections may exceed tens of thousands. Therefore, we have to optimize the wire routing and interconnections and thus determine the efficient designs. Kernighan-Lin algorithm, traveling salesman problem, simulated annealing algorithm and single row routing problem are used to find the best design. Included here are some simple examples to find the results. A simulation program using Microsoft Visual C++ is developed to simulate the single row routing problem using the simulated annealing algorithm. Keywords: Placement and Routing in VLSI; Single Row Routing; Kernighan-Lin Algorithm; Simulated Annealing

This paper presents algorithms whose input is an undirected graph, and whose output is a tree decomposition of width that approximates the optimal, the treewidth of that graph. The algorithms differ in their computation time and their approximation guarantees. The first algorithm works in polynomial-time and finds a factor-O(log OPT) approximation, where OPT is the treewidth of the graph. This is the first polynomial-time algorithm that approximates the optimal by a factor that does not depend on n, the number of nodes in the input graph. As a result, we get an algorithm for finding pathwidth within a factor of O(log OPT⋅log n) from the optimal. We also present algorithms that approximate the treewidth of a graph by constant factors of 3.66, 4, and 4.5, respectively and take time that is exponential in the treewidth. These are more efficient than previously known algorithms by an exponential factor, and are of practical interest. Finding triangulations of minimum treewidth for graphs is central to many problems in computer science. Real-world problems in artificial intelligence, VLSI design and databases are efficiently solvable if we have an efficient approximation algorithm for them. Many of those applications rely on weighted graphs. We extend our results to weighted graphs and weighted treewidth, showing similar approximation results for this more general notion. We report on experimental results confirming the effectiveness of our algorithms for large graphs associated with real-world problems.

An ordered binary decision diagram (OBDD) is a directed acyclic graph that represents a Boolean function. Since OBDDs have many nice properties as data structures, they have been extensively studied for decades in both theoretical and practical fields, such as VLSI (Very Large Scale Integration) design, formal verification, machine learning, and combinatorial problems. Arguably, the most crucial problem in using OBDDs is that they may vary exponentially in size depending on their variable ordering (i.e., the order in which the variables are to be read) when they represent the same function. Indeed, it is NP hard to find an optimal variable ordering that minimizes an OBDD for a given function. Friedman and Supowit provided a clever deterministic algorithm with time/space complexity O^∗(3ⁿ), where n is the number of variables of the function, which is much better than the trivial brute-force bound O^∗(n!2ⁿ). This paper shows that a further speedup is possible with quantum computers by presenting a quantum algorithm that produces a minimum OBDD together with the corresponding variable ordering in O^∗(2.77286ⁿ) time and space with an exponentially small error probability. Moreover, this algorithm can be adapted to constructing other minimum decision diagrams such as zero-suppressed BDDs.

Given a graph G=(V,E), graph bisection is the problem of finding a partition of the vertex set V in two equal-sized subsets V/sub 1/ and V/sub 2/ so that the number of edges between them is minimized. This problem has important applications in circuit partitioning, testing, VLSI design and other network-related problems that apply the divide-and-conquer strategy. The authors introduce a new heuristic approach, called iterative compaction (IC), which employees a node degree based matching and iterative graph compaction. This gives a significant improvement over the performance of known bisection algorithms in both time and quality of the results. >

Multiobjective network topology design

This paper describes recent and planned work at Stanford University in applying database technology to the problems of VLSI design. In particular, it addresses the issue of communication within a design's different representations and hierarchical levels in a multiple designer environment. We demonstrate the heretofore questioned utility of using commercial database systems, at least while developing a versatile, flexible, and generally efficient model and its associated communication paths. Completed work and results from initial work using DEC DBMS-20 is presented, including macroexpansion within the database, and signaling of changes to higher structural levels. Considerable discussion regarding overall philosophy for continued work is also included.

The paper discusses a modified algorithm based on the ants’ behavior in nature. We suggest to apply this algorithm for solving the element placement problem—one of the most difficult problem in the VLSI design. This problem belongs to the NP-class problem that is there are no precise methods to solve this problem. Also we formulate the placement problem and choose an optimization criterion. The developed ant colony optimization (ACO) algorithm obtains optimal and quasi-optimal solutions during polynomial time. The distinguish feature of the algorithm is that alternative solution are represented as an undirected graph with weighted edges. Besides, at each generation the algorithm creates a taboo-list to eliminate the quantity of agent (ant) which is wrong from the point of view the using of Reverse Polish notation. To compare obtained results with known analogous algorithms we developed software which allows to carry out experiments on the basis of IBM benchmarks. Conducted experiments shown that the ACO algorithm is better than the other algorithms an average of 9 %.

A novel via minimization approach is presented for two-layer routing of printed-circuit boards and VLSI chips. The authors have analyzed and characterized different aspects of the problem and derived an equivalent graph model for the problem from the linear-programming formulation. Based on the analysis of their unified formulation, the authors pose a practical heuristic algorithm. The algorithm can handle both grid-based and gridless routing. Also, an arbitrary number of wires is allowed to intersect at a via, and both Manhattan and knock-knee routings are allowed. >

Due to increasing design complexity, routing congestion has become a critical problem in VLSI designs. This paper introduces a distributed metric to predict routing congestion for a premapped netlist and applies it to technology mapping that targets area optimization. Our technology mapping algorithm is guided by a probabilistic congestion map for the subject graph to identify the congested regions. Experimental results on the benchmark circuits in a 90nm technology show that congestion-aware mapping results in a reduction of 37%, on an average, in track overflows as compared to conventional technology mapping.

In the past few decades, there has been a large amount of work on algorithms for linear network flow problems, special classes of network problems such as assignment problems (linear and quadratic), Steiner tree problems, topology network design and nonconvex cost network flow problems. Network optimization problems find numerous applications in transportation, in communication network design, in production and inventory planning, in facilities location and allocation, and in VLSI design. The purpose of this book is to cover a spectrum of recent developments in network optimization problems, from linear networks to general nonconvex network flow problems.