Spectral decision diagrams using graph transformations

This special issue of the VLSI DESIGN: an International Journal of Custom-Chip Design, Simulation and Testing is devoted to spectral techniques, new types of decision trees and diagrams, their applications, efficient ways of their calculation and mutual relations between spectral techniques and classical decision diagrams. Manipulations and calculations with discrete functions are fundamental tasks in many areas of Computer Science and Engineering. Many problems in digital system design, simulation and testing can be expressed as a sequence of operations on discrete functions. The performance of Computer-Aided Design systems used in solving various problems in this area strongly depends on the efficiency of representations of discrete functions. Decision Diagrams (DDs) have proved very convenient data structure for discrete function representations, permitting manipulations and calculations with large functions efficiently in terms of time and space. In many applications, as for example those involving large matrices, conventional algorithms are significantly improved by using DDs. In logic design, such applications relate to basic problems of the design, verification, simulation and testing logical networks. Besides Boolean functions, some other types of discrete representations, such as multi-valued functions, cube sets, EXOR-based spectral and probabilistic formulas have to be dealt with. Hence the numbers of different decision trees and diagrams have been introduced for these various applications and representations. The spectral or polynomial representation of Boolean function is obtained by expressing it in terms of an orthogonal basis. The most popular basis is formed by discrete Walsh functions. Note that the spectral and the polynomial representation of a Boolean function are equivalent. The discrete orthogonal functions are referred to as the basis functions when the spectral or abstract harmonic terminology is used and as monomials when the polynomial terminology is used. Such polynomial representations have extensive applications in coding theory and cryptography as well as design of nonlinear filters. Spectral techniques based on Walsh, Haar, Arithmetic and Reed–Muller transforms have been used in digital logic design for more than 30 years. These techniques have been used for Boolean function classification, disjoint decomposition, identification of symmetries, parallel and serial linear decomposition, spectral translation synthesis (extraction of linear preand post-filters), multiplexer synthesis, threshold logic synthesis, state assignment and testing, and evaluation of logic complexity. The renewed interest in applications of spectral methods in design of VLSI digital circuits is caused by their excellent design for testability properties and in their efficiency in Boolean mapping problems. Furthermore, the practical applicability of these techniques was greatly improved with the development of efficient methods that allow calculating and operating on spectra of Boolean functions directly from reduced representations of such functions in the form of arrays of cubes or decision diagrams. Following from these recent developments, techniques have been presented for efficient spectral translation to decompose a circuit into a cascade of two sub circuits: linear block composed of EXOR gates fed by the primary input of the overall circuit. Such linear decomposition drastically simplifies the synthesis task. The choice of suitable linear transformation is based on a complexity measure assigned to each Boolean function that is heuristically related to the complexity of the final circuit implementation. To avoid the experimental costs of computing the Walsh transform, Binary Decision Diagrams (BDDs) based techniques are used. Recently the idea of linear transformations is applied to decision diagrams. By combining powerful spectral linear techniques with variable reordering techniques, it is possible to synthesize large Boolean functions with standard Computer-Aided Design tools that fail otherwise. The areas addressed by this special issue span spectral transforms, their applications and efficient calculation methods through decision diagrams. New spectral decision diagrams are also emerging that support larger data structures allowing more complex discrete representations to be implemented that was previously impossible.

In this paper, we present methods for eliminating higher-order quantifiers in proof goals arising in the verification of digital circuits. For the description of the circuits, a subset of higher-order logic called hardware formulae is used which is sufficient for describing hardware specifications and implementations at register transfer level. Real circuits can be dealt with as well as abstract (generic) circuits. In case of real circuits, it is formally proved, that the presented transformations result in decidable formulae, such that full automation is achieved for them. Verification goals of abstract circuits can be transformed by the presented methods into goals of logics weaker than higher-order logic, e.g. (temporal) propositional logic. The presented transformations are also capable of dealing with hierarchy and have been implemented in HOL90.

In this paper we proposed unconventional method for the synthesis of digital current circuits based on linear algebra. The novelty of the material lies in the linear-monotonic version of the representation of multi-valued functions. The mathematical analysis of expressions of the monotonic form of the logical-arithmetic representation is carried out, as well as schematic implementations and graphic designations of considered logical functions are shown. The functional diagram of the current memory element is presented.

Given a Boolean function f on n variables, a Disjoint Sum-of-Products (DSOP) of f is a set of products (ANDs) of subsets of literals whose sum (OR) equals f, such that no two products cover the same minterm of f. DSOP forms are a special instance of partial DSOPs, i.e. the general case where a subset of minterms must be covered exactly once and the other minterms (typically corresponding to don’t care conditions of f) can be covered any number of times. We discuss finding DSOPs and partial DSOPs with a minimal number of products, a problem theoretically connected with various properties of Boolean functions and practically relevant in the synthesis of digital circuits. Finding an absolute minimum is hard, in fact we prove that the problem of absolute minimization of partial DSOPs is NP-hard. Therefore it is crucial to devise a polynomial time heuristic that compares favorably with the known minimization tools. To this end we develop a further piece of theory starting from the definition of the weight of a cube c as a functions of the number of fragments induced on other cubes by the selection of c, and show how cube weights can be exploited for building a class of minimization heuristics for DSOP and partial DSOP synthesis. A set of experiments conducted on major benchmark functions show that our method, with a family of variants, always generates better results than the ones of previous heuristics, including the method based on a BDD representation of f.

Today, the most common abstraction level for manual design capture is at the so called register transfer level. At this level, all synchronous registers, latches and the combinational logic between the sequential elements are described in a hardware description language such as Verilog or VHDL. The description is then transformed into logic gate implementations based on a technology specific cell library, a procedure known as logic synthesis. This allows a designer to handle more complex design because detailed manual analysis need not be made at the logic gate level that is more tedious and error prone. Register transfer level is certainly not the only starting point for automated hardware synthesis. The analysis and synthesis of digital circuits are still being pushed toward even higher level of abstraction for manual manipulation. For example, macro block level specification and synthesis has been practiced in some design areas. The register transfer and macro block level design methodologies are part of the architecture and system level techniques to be discussed in this chapter.

Traditionally, the problems of binding and placement in the synthesis of digital circuits have been formulated and solved separately. However, placement and binding strongly interact and design decisions taken during these phases determine the interconnect structure. As feature sizes continue to decrease, the delay caused by signal propagation through interconnect more and more dominate the overall system performance. Hence, optimizing interconnect becomes increasingly important. In this paper, we propose for the first time an analytical approach to capture the placement and binding problems in a single, unified Mixed Integer Linear Programming (MILP) model which also allows minimizing the overall interconnect structure. Such a model can serve as a starting point for deriving efficient heuristics in that it captures all information required for a comprehensive analysis of the problem. The target architecture is a linear bit-slice datapath, however, the model can be easily extended to handle two-dimensional datapath models.

Variability in circuit delay is a significant challenge in the design and synthesis of digital circuits. While the challenge is being addressed at various levels of the design hierarchy, we argue that modern register-transfer level (RTL) synthesis tools can be enhanced to deal with this problem in an alternate, yet effective, manner. Our solution involves the design of variability- tolerant, correct circuits assuming common-case, rather than worst-case, values for critical path delays. We propose a methodology to design variability-tolerant circuits that can, at runtime, detect and efficiently recover from delay errors, which would be inevitably introduced due to the use of common-case delay values. Variability-agnostic designs are automatically transformed into variability-tolerant circuits by the introduction of shadow logic to detect and recover from runtime errors, while exploiting data speculation to derive performance benefits. For various benchmark circuits, we show that the area overhead imposed by our scheme is only 11.4% on an average, while achieving upto 16.3% performance speedup over margined designs.

The development of practical methods for synthesis and verification of complex photonic circuits presents a grand challenge for the nascent field of quantum engineering. Of course, classical electrical engineering provides essential foundations and serves to illustrate the degree of sophistication that can be achieved in automated circuit design. In this paper, we explore the utility of term rewriting approaches to the transformation of quantum circuit models, specifically applying rewrite rules for both reduction/verification and robustness analysis of photonic circuits for autonomous quantum error correction. We outline a workflow for quantum photonic circuit analysis that leverages the Modelica framework for multidomain physical modeling, which parallels a previously described approach based on VHSIC Hardware Description Language (VHDL).

Researchers are looking for alternatives to overcome the upcoming limits of conventional hardware technologies. Reversible logic thereby established itself as a promising direction so that several methods for synthesis, verification, and testing of reversible circuits have already been proposed. However, also methods for debugging, i.e., to determine error candidates in case of a failed verification, are required to complete the design flow. Even if first approaches have already been proposed, debugging of reversible circuits still is in the beginning. In this paper, we present an alternative method to automatically debug reversible circuits. We thereby focus on missing control errors -- an established error model in the design of reversible circuits. A new notion of an error candidate is proposed that relies on the observation of a necessary condition for error locations in reversible circuits. Using this notion, a set of error candidates is obtained that differs from the error candidates returned by previous methods. Thus, combining the approaches enhances the overall debugging flow. Experimental results demonstrate that a higher accuracy is obtained in significantly shorter run-time.

Evolvable Hardware (EHW) applications have, so far, encompassed the synthesis of standard analog and digital circuits' building blocks through Genetic Algorithms (GAs). Currently, the research effort in EHW is being driven towards twofold purposes: the synthesis of circuits of medium to high complexity; and the design of reconfigurable architectures that facilitate the system evolvability and on-chip implementation of the evolved circuits. This work addresses these issues by describing the evolution of Digital to Analog Converters (DACs). We investigate the efficiency of the evolutionary system when using different representations and when evolving current and voltage mode circuits. A new technique based on hierarchical evolution is devised to enhance the evolutionary speed and the design scalability. New methods to increase the competitiveness of the evolved designs are also discussed.

With the rapid growth in the size and complexity of digital circuits, the possibility of bug occurrence has significantly increased. In order to avoid the enormous financial loss due to the production of buggy circuits, using scalable formal verification methods is essential. The scalability of a verification method for a specific design is proven by showing that the method has polynomial space and time complexities. Unfortunately, not all verification methods have a polynomial complexity, particularly when it comes to the verification of large and complex designs. In this paper, we propose a divide-and-conquer strategy for Polynomial Formal Verification (PFV) of complex circuits. Instead of using a monolithic proof engine to verify the entire design, we break the verification task down into several problems, which can be solved in polynomial space and time using a hybrid proof engine. As a case study, we investigate the PFV of the ALU in a RISC-V processor using our divide-and-conquer strategy.

As VLSI fabrication technology progresses to 65 nm feature sizes and smaller, transistors no longer operate as ideal switches. This motivates the verification of digital circuits using continuous models. Recently, we showed how such verification can be performed using projection based methods.However, the verification was slow, requiring nearly four CPU days to verify a nine-transistor toggle flip-flop. Here, we describe improvements to the reachability algorithms and optimizations of the software architecture. These produce a 15 x reduction in computation time and significant reductions in the overapproximation errors. With these changes, the same toggle flip-flop can be verified in a few hours, making formal verification a viable alternative to circuit simulation.

We introduce a framework for the formal specification and verification of\nquantum circuits based on the Feynman path integral. Our formalism, built\naround exponential sums of polynomial functions, provides a structured and\nnatural way of specifying quantum operations, particularly for quantum\nimplementations of classical functions. Verification of circuits over all\nlevels of the Clifford hierarchy with respect to either a specification or\nreference circuit is enabled by a novel rewrite system for exponential sums\nwith free variables. Our algorithm is further shown to give a polynomial-time\ndecision procedure for checking the equivalence of Clifford group circuits. We\nevaluate our methods by performing automated verification of optimized\nClifford+T circuits with up to 100 qubits and thousands of T gates, as well as\nthe functional verification of quantum algorithms using hundreds of qubits. Our\nexperiments culminate in the automated verification of the Hidden Shift\nalgorithm for a class of Boolean functions in a fraction of the time it has\ntaken recent algorithms to simulate.\n

When ICCAD began in 1983, we had no robust tools for device modelling, analog circuit synthesis, electrical timing simulation, transistor-to-logic abstraction, or large-scale custom circuit tuning. Today, all these techniques are in common industrial usage, most commercially available. The seven papers in this section fundamentally transformed the way in which we model, manipulate, and solve these difficult tasks today. They are linked by a common thread of “deep circuits innovation”.

Speed-independent circuits offer a potential solution to the timing problems of VLSI. In this book David Dill develops and implements a theory for practical automatic verification of these control circuits. He describes a formal model of circuit operation, defines the proper relationship between an implementation and its specification, and constructs a computer program that can check this relationship. Asynchronous or speed-independent circuit design has gained renewed interest in the VLSI community because of the possibilities it provides for dealing with problems that arise with the increasing complexity of VLSI circuits. Speed-independent circuits offer a way around such phenomena as clock skew, which can be a serious obstacle in the design of large systems. They can expedite circuit design by reducing design time and simplifying the overall process. A major challenge to the successful utilization of speed-independent circuits is correctness. The verification method described here insures that a design is correct and because it can be automated it is a significant advantage over manual verification. Dill proposes two distinct theories - prefix-closed trace structures, which can model and specify safety properties, and complete trace structures, which can also deal with liveness and fairness properties. Trace Theory for Automatic Hierarchical Verification of Speed Independent Circuits is a 1988 ACM Distinguished Dissertation