Synthesis and Circuitry of Multi-Valued Digital Current Logic Elements: “Classical” Linear-Monotonic Approach

In scientific publications and conducted studies, the possibility of representing logical functions (LF) in alternative forms of representation is demonstrated, the characteristic feature of which is a polynomial entity, which reduces to the representation of LF in the form of series different from the traditional classical representation by adding members of a series - in particular, for an algebraic form, the addition is carried out algebraically with weight coefficients, and in the case of the use of the Reed-Muller form addition is made for mod 2. The results of complete sets of logical functions studies proved that the traditional classical form does not always ensure the minimality of indicators for the structural complexity of the logical functions implementation, which makes relevant further steps in determining the optimal forms for representing logical functions in the problems of discrete devices analysis and synthesis. The implementation of the combination scheme for a given logical function from n arguments is carried out by some set of variants of structures. In problems of analysis and synthesis of combinational circuits of discrete devices it is necessary to evaluate the quality of their possible structures, to provide identification and selection of the most successful or optimal ones. The concept of the logical functions optimal form of representation is presented in the article as an important direction of structural perfection of discrete devices on the basis of their logical functions realization in alternative forms of representation. The existence of the OFR-concept, which takes into account different forms of representation, makes it highly efficient to use alternative forms of logical functions representation from the point of the structural complexity parameters of the combinational schemes implementation in comparison with traditional classical form. The article outlines the factors for the further improvement of the OFR-concept by filling it with new scientific achievements, which will allow to completely or partially remove difficulties with the introduction of the optimal FR into broad engineering practice

Evolvable Hardware (EHW) applications have, so far, encompassed the synthesis of standard analog and digital circuits' building blocks through Genetic Algorithms (GAs). Currently, the research effort in EHW is being driven towards twofold purposes: the synthesis of circuits of medium to high complexity; and the design of reconfigurable architectures that facilitate the system evolvability and on-chip implementation of the evolved circuits. This work addresses these issues by describing the evolution of Digital to Analog Converters (DACs). We investigate the efficiency of the evolutionary system when using different representations and when evolving current and voltage mode circuits. A new technique based on hierarchical evolution is devised to enhance the evolutionary speed and the design scalability. New methods to increase the competitiveness of the evolved designs are also discussed.

Spectral techniques are powerful methods for synthesis and verification of digital circuits. The advances in DD representations for discrete valued functions in terms of computational efficiency can be exploited in the calculation of the spectra of Boolean functions. The classical approach in computing the spectrum of a function by taking advantage of factored transformation matrices as used in the FFT may be reformulated in terms of DD based graph algorithms resulting in a complete representation of the spectrum. The relationship between DD based interpretations and the linear algebra based definitions of spectral methods are described.

During computer-aided design, the problem of how to determine the logical function of a digital circuit arises in many contexts. For example, assigning functional meaning to a circuit is a fundamental operation in both reverse engineering and implementation validation. This report describes such a determination by discussing how a higher-level functional representation is constructed from a detailed circuit description (i.e., a gate-level netlist, which is a list of logic gates and their interconnections). The approach used involves transforming parts of the netlist into a functional representation and then manipulating this representation. Two types of functional representations are described: (1) a mathematical representation based on the logical operators ``exor`` and ``and`` and (2) a directed acyclic graph representation based on binary decision trees. Each representation provides a canonical form of the logical function being implemented (i.e., a form that is independent of implementation details). Such forms, however, have a well-known problem associated with the ordering of inputs: for each order, a unique form exists. A solution to this problem is given for both representations. Experimental results that demonstrate the use of these representations in the process of assigning functional meaning to a circuit are provided. The report also identifies and discusses issues critical to the performance required of this fundamental operation.

Modem microelectronic technology.gives opportunities to build digital circuits of huge complexity and provides a wide diversity of logic building blocks. Although logic designers have been building circuits for many years, they have realized that advances in microelectronic technology are outstripping their abilities to make use of the created opportunities. In this paper, we present the fundamentals of a logic design methodology which meets the requirements of today′s complex circuits and modem building blocks. The methodology is based on the theory of general full‐decompositions which constitutes the theory of digital circuit structures at the highest abstraction level. The paper explains the theory and shows how it can be used for digital circuit synthesis. The decomposition methodology that is presented ensures “correctness by construction” and enables very effective and efficient post‐factum validation. It makes possible extensive examination of the structural features of the required information processing in relation to a given set of objectives and constraints.

Today, the most common abstraction level for manual design capture is at the so called register transfer level. At this level, all synchronous registers, latches and the combinational logic between the sequential elements are described in a hardware description language such as Verilog or VHDL. The description is then transformed into logic gate implementations based on a technology specific cell library, a procedure known as logic synthesis. This allows a designer to handle more complex design because detailed manual analysis need not be made at the logic gate level that is more tedious and error prone. Register transfer level is certainly not the only starting point for automated hardware synthesis. The analysis and synthesis of digital circuits are still being pushed toward even higher level of abstraction for manual manipulation. For example, macro block level specification and synthesis has been practiced in some design areas. The register transfer and macro block level design methodologies are part of the architecture and system level techniques to be discussed in this chapter.

Traditionally, the problems of binding and placement in the synthesis of digital circuits have been formulated and solved separately. However, placement and binding strongly interact and design decisions taken during these phases determine the interconnect structure. As feature sizes continue to decrease, the delay caused by signal propagation through interconnect more and more dominate the overall system performance. Hence, optimizing interconnect becomes increasingly important. In this paper, we propose for the first time an analytical approach to capture the placement and binding problems in a single, unified Mixed Integer Linear Programming (MILP) model which also allows minimizing the overall interconnect structure. Such a model can serve as a starting point for deriving efficient heuristics in that it captures all information required for a comprehensive analysis of the problem. The target architecture is a linear bit-slice datapath, however, the model can be easily extended to handle two-dimensional datapath models.

Variability in circuit delay is a significant challenge in the design and synthesis of digital circuits. While the challenge is being addressed at various levels of the design hierarchy, we argue that modern register-transfer level (RTL) synthesis tools can be enhanced to deal with this problem in an alternate, yet effective, manner. Our solution involves the design of variability- tolerant, correct circuits assuming common-case, rather than worst-case, values for critical path delays. We propose a methodology to design variability-tolerant circuits that can, at runtime, detect and efficiently recover from delay errors, which would be inevitably introduced due to the use of common-case delay values. Variability-agnostic designs are automatically transformed into variability-tolerant circuits by the introduction of shadow logic to detect and recover from runtime errors, while exploiting data speculation to derive performance benefits. For various benchmark circuits, we show that the area overhead imposed by our scheme is only 11.4% on an average, while achieving upto 16.3% performance speedup over margined designs.

Given a Boolean function f on n variables, a Disjoint Sum-of-Products (DSOP) of f is a set of products (ANDs) of subsets of literals whose sum (OR) equals f, such that no two products cover the same minterm of f. DSOP forms are a special instance of partial DSOPs, i.e. the general case where a subset of minterms must be covered exactly once and the other minterms (typically corresponding to don’t care conditions of f) can be covered any number of times. We discuss finding DSOPs and partial DSOPs with a minimal number of products, a problem theoretically connected with various properties of Boolean functions and practically relevant in the synthesis of digital circuits. Finding an absolute minimum is hard, in fact we prove that the problem of absolute minimization of partial DSOPs is NP-hard. Therefore it is crucial to devise a polynomial time heuristic that compares favorably with the known minimization tools. To this end we develop a further piece of theory starting from the definition of the weight of a cube c as a functions of the number of fragments induced on other cubes by the selection of c, and show how cube weights can be exploited for building a class of minimization heuristics for DSOP and partial DSOP synthesis. A set of experiments conducted on major benchmark functions show that our method, with a family of variants, always generates better results than the ones of previous heuristics, including the method based on a BDD representation of f.

We propose and demonstrate a design methodology for embedded systems satisfying low power requirements suitable for self-powered sensor and actuator nodes. This design methodology focuses on 1. smart energy management at runtime and 2. application-specific System-On- Chip (SoC) design at design time, contributing to low-power systems on both algorithmic and technology level. Smart energy management is performed spatially at runtime by a behaviour-based or state-action-driven selection from a set of different (implemented) algorithms classified by their demand of computation power, and temporally by varying data processing rates. It can be shown that power/energy consumption of an application-specific SoC design depends strongly on computation complexity. Signal and control processing is modelled on abstract level using signal flow diagrams. These signal flow graphs are mapped to Petri Nets to enable direct high-level synthesis of digital SoC circuits using a multi-process architecture with the Communicating-Sequential-Process model on execution level. Power analysis using simulation techniques on gatelevel provides input for the algorithmic selection during runtime of the system, leading to a closed-loop design flow. Additionally, the signal-flow approach enables power management by varying the signal flow and data processing rates depending on actual energy consumption, estimated energy deposit, and required Quality-of-Service.

Evolvable Hardware arises as a promising solution for automatic digital synthesis of digital and analog circuits. During the last decade, a special interest has been focused on evolving digital systems by directly mapping a chromosome on the FPGA configuration bitstream. This approach allowed a great degree of flexibility for evolving circuits. Nowadays, FPGAs routing scheme does not allow doing it in such flexible and safe way, so additional constraints must be introduced. In this paper we summarize three techniques for performing hardware evolution by exploiting the capacities of Virtex families. Among our proposals there are high and low level approaches, and coarse and fine grained components. A modular based evolution, with pre-placed and routed components, provides a coarse grain approach. Two techniques for directly modifying LUT contents on hard macros provide a fine grained evolution. Finally, integrating both approaches, coarse and fine grain, provides a more general and powerful framework.

Analysis and Synthesis of Digital Logic Circuits

An approach to logic synthesis of digital synchronous sequential circuits is presented. Algorithms are described for minimizing the area of synchronous combinational and/or sequential circuits under cycle time constraints and for minimizing the cycle time under area constraints. It is shown how to optimize concurrently the circuit equations and the register position by a set of algorithms based on logic transformations. An implementation of the algorithms in the program Minerva is described, and experimental results are reported.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A new approach is presented to logic synthesis of digital synchronous sequential circuits. The authors describe algorithms for minimizing (i) the area of synchronous combinational and/or sequential circuits under cycle time constraints, and (ii) the cycle time under area constraints. Previous approaches attacked this problem by separating the combinational logic from the registers and by applying circuit transformations to the combinational component only. The authors show instead how to optimize concurrently the circuit equations and the register position. This method is novel and can achieve results that are at least as good as those obtained by previous methods. A computer implementation of the algorithms in the Minerva program is described. >

This paper primarily focuses on Gate Diffusion Input (GDI) technique used for the implementation of digital logic circuits. It also discusses in detail the limitations and modifications of the basic GDI technique. Initially, GDI was a new technique used for low power digital combinational circuit design. This approach provides a reduction in power consumption, propagation delay, and area of digital circuits while the logic design complexity is small. GDI methodology allows implementation of a wide range of complex logic functions using only two transistors. GDI is a new technique for digital circuits implementation with a lot of advantages over existing ones. This paper also analyzes the recent applications of GDI technique which are the implementation of MASH 1-1 and MOD 2 modulator for Sigma Delta DACs and development of full adders for efficient arithmetic operations.