Speed-path analysis for multi-path failed latches with random variation

A double edge clipping technique is proposed for at-speed BIST testing. It differs from traditional circuit delay testing techniques by changing the clock rate using external ATE. This method uses lower-speed input clock frequency, then applies internal BIST circuit to adjust clock edges for circuit at-speed delay testing and speed binning. This built-in at-speed delay test with calibration mechanism named as double edge clipping (DEC) technique. DEC is based on the lunch on shift (LOC) scheme by precisely controlling the launch and capture edges during delay test operation. Two wide-range (26% -80%), fine-scale (16ps) duty cycle adjustment circuits with high-precision (28ps) calibration mechanism are effective applied for at-speed delay testing and performance binning. The key to DEC testing technique is to generate a pair of clock pulses for the launch and capture events. Two DCPG provide adjusted positive clock edge during test operation. DEC uses 500kHz low speed input clock then provides working clock frequency from 197MHz to 932MHz.

Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonstrating the applicability of at-speed testing and its effect on test length. >

To guarantee that an application-specific integrated circuit (ASIC) meets its timing requirement, at-speed scan testing becomes an indispensable procedure for verifying the performance of ASIC. However, at-speed scan test suffers the test-induced yield loss. Because the switching-activity in test mode is much higher than that in normal mode, the switching-induced large current drawn causes severe IR drop and increases gate delay. X-filling is the most commonly used technique to reduce IR-drop effect during at-speed test. However, the effectiveness of X-filling depends on the number and the characteristic of X-bit distribution. In this paper, we propose a physical-location-aware X-identification which redistributes X-bits so that the maximum switching-activity is guaranteed to be reduced after X-filling. We estimate IR-drop using RedHawk tool and the experimental results on ITC'99 show that our method has an average of 9.42% more reduction of maximum IR-drop as compared to a previous work which redistributes X-bits evenly in all test vectors.

This paper presents a novel test point insertion method for pseudo-random built -in self-test (BIST) to reduce the area overhead. R ecently, a new test point insertion method for BIST was proposed which tries to use functional flip -flops to drive control test points instead of adding extra dedicated flip - flops for driving the control points. Replacement rule used in the previous work has limitations preventing some dedicated flip-flops from being replaced by functional flip -flops. This paper proposes a logic cone analysis based test point insertion approach to overcome the limitations. Logic cone analysis is performed to find candida te functional flop -flops for replacing dedicated flip -flops. Experimental results indicate that the proposed method reduces test point area overhead significantly with minimal loss of testability by replacing the dedicated flip - flops. application to the inputs of the circuit -under-test (CUT). The output response analyzer compacts the output response of the CUT into a signature. T his provides a variety of benefits including the ability to apply a large number of test patterns in a short time (i.e., shorter test time) , at-speed testing, minimal automatic test equipment (ATE) storage requirements, test application in the field over t he lifetime of the part, and a reusable test solution for embedded cores. In particular, BIST is crucial for applications such as aerospace, defense, automotive, computer, etc., for the reliability of the entire system. The most economical logic BIST te chniques are based on pseudo-random pattern testing. On -chip input pattern generator constructed from a linear feedback shift register (LFSR) is most commonly used to generate pseudo -random patterns with its compact structure. And on -chip output response analyzer compacts the output responses into a signature and this allows significant compaction of test data. Pseudo-random pattern testing also can achieve high coverage of non-modeled faults which are not explicitly targeted during deterministic test ge neration. However, a major challenge is the presence of random -pattern-resistant (r.p.r.) faults which have low detection probabilities and hence may limit the fault coverage that can be achieved with pseudo -random patterns. There have been many research efforts to overcome the fault coverage limitation by r.p.r faults. Mainly two directions are given to enhance the fault coverage. One is to modify the pattern generator in order to generate patterns that detect hard faults. Various methods have been pr oposed such as weighted pattern generation ( 2), (4)-(8), pattern mapping ( 9)- (11), bit-fixing (12), bit-flipping (13), and LFSR reseeding (14)-(19).

A design approach for video signal processors is presented that is driven by characteristics of the algorithms, rather than by technological enhancements to conventional microprocessor-style DSP architectures. The goal of this algorithm-driven approach is the design of processors that possess not only the flexibility to execute several algorithms, but an order of magnitude lower complexity than conventional processors. This design approach is applied to the design of a high-speed signal processor targeted at video compression algorithms including the 8/spl times/8 DCT, wavelet/subband coding, and vector quantization. The fabricated processor chip can execute each algorithm at up 25 MPixels/sec and has been implemented with only 80,000 transistors in a 1.2-/spl mu/m CMOS process. >

High power consumption during at-speed delay fault testing may lead to yield loss and premature aging. On the other hand, reducing too much test power might lead to test escape and reliability problems. Thus, to avoid these issues, test power has to map the power consumed during functional mode. Existing works target the generation of functional test programs able to maximize the power consumption in functional mode of microprocessor cores. The obtained power consumption will be used as threshold to tune the power consumed during testing. This paper investigates the impact of re-using such functional test programs for testing purposes. We propose to apply them by exploiting existing DfT architecture to maximize the delay fault coverage. Then, we combine them with the classical at-speed LOC and LOS delay fault testing schemes to further increase the fault coverage. Results show that it is possible to achieve a global test solution able to maximize the delay fault coverage while respecting the functional power budget.

The informational energy (IE) can be interpreted as a measure of average certainty. In previous work, we have introduced a non-parametric asymptotically unbiased and consistent estimator of the IE. Our method was based on the kth nearest neighbor (kNN) method, and it can be applied to both continuous and discrete spaces, meaning that we can use it both in classification and regression algorithms. Based on the IE, we have introduced a unilateral dependency measure between random variables. In the present paper, we show how to estimate this unilateral dependency measure from an available sample set of discrete or continuous variables, using the kNN and the naive histogram estimators. We experimentally compare the two estimators. Then, in a real-world application, we apply the kNN and the histogram estimators to approximate the unilateral dependency between random variables which describe the temperatures of sensors placed in a refrigerating room.

The impact of biological variation on postharvest behaviour of Belgian endive: The case of multiple stochastic variables

When analyzing data from scanning tunneling spectroscopy (STS) it is generally assumed that the density of states and local density of states (LDOS) are simply related with the current-voltage (I-V) curves. This assumption has been derived phenomenologically within the framework of theories developed for a variety of situations. We continue here with the development of a theory of STS with concrete applications for semiconducting samples, going beyond the traditional Bardeen approximation. As in previous works, our present model provides a current that is a sum over tip states of semiconductor local density of states modulated by tip-dependent coefficients. For a tungsten tip and silicon sample, we find that these coefficients are nonzero only for energies close to the Fermi energy. This makes the I-V curve closely follow the LDOS. On the other hand, we have found that the conductance-voltage curves present features derived from the Van Hove singularities of the semiconductor.

The problem of malicious inclusions in hardware is an emerging threat, and detecting them is a difficult challenge. In this research, we enhance an existing method for creating assertion-based dynamic checkers, and demonstrate how behavioral security requirements can be derived from a processor's architectural specification, then converted into security checkers that are part of the processor's design. The novel contributions of this research are: - We demonstrate the method using a set of assertions, derived from the architectural specification, on a full-scale open-source general-purpose processor design, called OpenRISC. Previous work used only a single assertion on a toy processor design. - We demonstrate the use of our checker-generator tool, called psl2hdl, which was created for this research. - We illustrate how the method can be used in concert with code coverage techniques, to either detect malicious inclusions or greatly narrow the search for malicious inclusions that use rare-event triggers.

The Pandora's Box problem and its extensions capture optimization problems with stochastic input where the algorithm can obtain instantiations of input random variables at some cost. To our knowledge, all previous work on this class of problems assumes that different random variables in the input are distributed independently. As such it does not capture many real-world settings. In this paper, we provide the first approximation algorithms for Pandora's Box-type problems with correlations. We assume that the algorithm has access to samples drawn from the joint distribution on input. Algorithms for these problems must determine an order in which to probe random variables, as well as when to stop and return the best solution found so far. In general, an optimal algorithm may make both decisions adaptively based on instantiations observed previously. Such fully adaptive (FA) strategies cannot be efficiently approximated to within any sub-linear factor with sample access. We therefore focus on the simpler objective of approximating partially adaptive (PA) strategies that probe random variables in a fixed predetermined order but decide when to stop based on the instantiations observed. We consider a number of different feasibility constraints and provide simple PA strategies that are approximately optimal with respect to the best PA strategy for each case. All of our algorithms have polynomial sample complexity. We further show that our results are tight within constant factors: better factors cannot be achieved even using the full power of FA strategies.

Consider a complete graph $K_n$ where the edges have costs given by independent random variables, each distributed uniformly between 0 and 1. The cost of the minimum spanning tree in this graph is a random variable which has been the subject of much study. This note considers the large deviation probability of this random variable. Previous work has shown that the log-probability of deviation by $\varepsilon$ is $-\Omega(n)$, and that for the log-probability of $Z$ exceeding $\zeta(3)$ this bound is correct; $\log {\rm Pr}[Z \geq \zeta(3) + \varepsilon] = -\Theta(n)$. The purpose of this note is to provide a simple proof that the scaling of the lower tail is also linear, $\log {\rm Pr}[Z \leq \zeta(3) - \varepsilon] = -\Theta(n)$.

Distributed Constraint Satisfaction (DisCSP) and Distributed Constraint Optimization (DCOP) are formal frameworks that can be used to model a variety of problems in which multiple decision-makers cooperate towards a common goal: from computing an equilibrium of a game, to vehicle routing problems, to combinatorial auctions. In this thesis, we independently address two important issues in such multi-agent problems: 1) how to provide strong guarantees on the protection of the privacy of the participants, and 2) how to anticipate future, uncontrollable events. On the privacy front, our contributions depart from previous work in two ways. First, we consider not only constraint privacy (the agents' private costs) and decision privacy (keeping the complete solution secret), but also two other types of privacy that have been largely overlooked in the literature: agent privacy, which has to do with protecting the identities of the participants, and topology privacy, which covers information about the agents' co-dependencies. Second, while previous work focused mainly on quantitatively measuring and reducing privacy loss, our algorithms provide stronger, qualitative guarantees on what information will remain secret. Our experiments show that it is possible to provide such privacy guarantees, while still scaling to much larger problems than the previous state of the art. When it comes to reasoning under uncertainty, we propose an extension to the DCOP framework, called DCOP under Stochastic Uncertainty (StochDCOP), which includes uncontrollable, random variables with known probability distributions that model uncertain, future events. The problem becomes one of making optimal offline decisions, before the true values of the random variables can be observed. We consider three possible concepts of optimality: minimizing the expected cost, minimizing the worst-case cost, or maximizing the probability of a-posteriori optimality. We propose a new family of StochDCOP algorithms, exploring the tradeoffs between solution quality, computational and message complexity, and privacy. In particular, we show how discovering and reasoning about co-dependencies on common random variables can yield higher-quality solutions.

Given a path in a spatial or temporal framework, we aim to find all contiguous subpaths that are both interesting (e.g., abrupt changes) and statistically significant (i.e., persistent trends rather than local fluctuations). Discovering interesting subpaths can provide meaningful information for a variety of domains including Earth science, environmental science, urban planning, and the like. Existing methods are limited to detecting individual points of interest along an input path but cannot find interesting subpaths. Our preliminary work provided a Subpath Enumeration and Pruning (SEP) algorithm to detect interesting subpaths of arbitrary length. However, SEP is not effective in avoiding detections that are random variations rather than meaningful trends, which hampers clear and proper interpretations of the results. In this article, we extend our previous work by proposing a significance testing framework to eliminate these random variations. To compute the statistical significance, we first show a baseline Monte-Carlo method based on our previous work and then propose a Dynamic Search-and-Prune (D-SAP) algorithm to improve its computational efficiency. Our experiments show that the significance testing can greatly suppress the noisy detections in the output and D-SAP can greatly reduce the execution time.

Functional test guarantees that the circuit is tested under normal conditions, thus avoiding any over-as well as under-test issues. This work is based on the use of Software-Based-Self-Test that allows a special application of functional test to the processor-based systems. This strategy applies the so-called functional test programs that are executed by the processor to guarantee a given fault coverage. The main goal of this paper is to investigate a methodology to improve the delay fault coverage of a given test set of functional test programs. We propose to exploit existing Design-for-Test architecture to apply in a smarter way the functional programs. Then, we combine those programs with the classical at-speed LOC and LOS delay fault testing schemes to further increase the delay fault coverage. Results show that it is possible to achieve a global test solution able to maximize the delay fault coverage.