Static Test Compaction for Scan-Based Designs to Reduce Test Application Time

Available register-transfer level (RTL) test generation techniques do not make a concerted effort to reduce the test application time associated with the derived tests. Chip tester memory limitations, increasing tester costs, etc., make it imperative that the issue of generating compact tests at the RTL be addressed and consolidated with the known gains of high-level testing. In this paper, the authors provide a comprehensive framework for generating compact tests for an RTL circuit. They develop a series of techniques that exploit the inherent parallelism available in symbolic test(s) derived for RTL module(s). These techniques enable them to schedule testing of multiple modules in parallel as well as perform test pipelining. In addition, the authors also present design for testability (DFT) techniques for lowering test application time. Using a maximum bipartite matching formulation, they choose a low-overhead set of test enhancements that can achieve compact tests. The authors' techniques can seamlessly plug into any generic high-level test framework. Their experimental results in the context of one such framework indicate that the proposed methodology achieves an average reduction in test application time of 54.2% for the example circuits.

The reduction of test application time for the general scan designed circuits has been studied. The reduction problem is investigated from three aspects: the test generation, selective scans, and rearrangement of scan path. The two phase testing strategy has been proposed to employ scan only for the hard-to-detect faults. Four cases of selective scan have also been identified. Furthermore, an ordering heuristic without layout constraint has been proposed to maximize the reduction of unnecessary scans and hence the test application time. Applying these reduction methods, the total test clock-cycles can be reduced to only 20% on average for ISCAS sequential benchmark circuits with partial scan. >

In this paper, we propose a method of test compression for multiple scan designs. Instead of the conventional serial scan chains, the proposed method constructs scan trees in which scan flip-flops are placed and routed in a tree structure. Inputs of the scan trees drive several scan trees of different lengths (height). Since test data volume and test application time are dominated by the scan tree with the maximum height among the constructed scan trees, the proposed method distributes the scan flip-flops to the scan trees so as to minimize the maximum height of the scan trees. In addition, the proposed method modifies the given test vectors to maximize the reduction in test application time. Experimental results for ISCAS-89 benchmark circuits show that the proposed method could reduce, on the average, test data volume by 77% compared with the conventional multiple scan design. The scan tree construction enlarges the number of scan outputs required. However test data volume could be reduced by 66% even if the number of scan outputs is limited.

Short test sequences for synchronous sequential circuits are important in reducing test application time and memory requirements. In addition, dynamic test compaction, where heuristics to generate short test sequences are incorporated into the test generation process, may also reduce test generation time. This is due to the fact that a smaller number of test vectors needs to be generated. We present a dynamic test compaction procedure. The compaction heuristics we use are based on previously proposed static compaction techniques. Conventionally, static compaction is applied as a postprocessing step, after the test sequence has been generated. In the proposed procedure, static compaction techniques are used while the test sequence is being generated, to reduce the need for postprocessing, or static compaction. Compared to other dynamic compaction procedures that generate very short test sequences, the computational overhead involved in the proposed procedure is significantly lower, yet short test sequences are obtained. The proposed techniques can be incorporated into other test generation procedures, to reduce the test lengths they produce.

Integrated circuit (IC) chip designs relying on Random Access Scan (RAS) architecture for post-production structural tests typically provide lower test power dissipation, test data volume, and test application time comparedto the classical serial scan-based Design for Test (DFT) methodology. However, previous RAS schemes incur high signal routing and test area overheads relative to the serial scan way. Unlike serial scan schemes, previous RAS schemes have not been effectively combined with test compression to further reduce test application time and test data volume. Authors have already formally documented a locally addressed (segmented) and compressed Segmented RAS (SRAS) architecture with low area overhead and test application time. This paper describes the SRAS architecture in more detail and provides comparative experimental results. Area overhead is reduced using test access hierarchy (segmented), while adding compression to RAS lowers the test application time.

In this paper, we propose a novel test architecture called the pseudo-full scan (PFS) architecture to reduce test application time and power consumption simultaneously. We also present a test generation procedure to generate a set of test patterns that is suitable for the PFS architecture. The method reduces test application time and power consumption by (1) scanning only a fraction of the flip-flops, and (2) compressing the test vector sequence into a much shorter one. Experimental results show that our method has the advantages of reducing the test application time and power dissipation compared to the conventional scan methodology.

This paper presents a new test data compression technique based on a compression code that uses exactly nine codewords. In spite of its simplicity, it provides significant reduction in test data volume and test application time. In addition, the decompression logic is very small and independent of the precomputed test data set. Our technique leaves many don't-care bits unchanged in the compressed test set, and these bits can be filled randomly to detect non-modeled faults. The proposed technique can be efficiently adopted for single- or multiple-scan chain designs to reduce test application time and pin requirement. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

A test pattern compression scheme for test data volume and application time reduction is proposed. While compression reduces test data volume, the increased number of internal scan chains due to an on-chip, fixed-rate decompressor reduces test application time proportionately. Through on-chip decompression, both the number of virtual scan chains visible to the ATE and the functionality of the ATE are retained intact. Complete fault coverage is guaranteed by constructing the decompression hardware deterministically through analysis of the test pattern set.

Single input change (SIC) sequence for VLSI testing has been researched because of effectiveness to more test fault models and low power consumption testing. It is the high fault coverage in deterministic built-in self-test (BIST) with low test cost and short test application time. The sequential single input change (SSIC) sequence used in deterministic BIST is presented in this paper for decreasing the dynamic power, reducing test application time and increasing fault coverage. The selection of seed vectors is the significant technique in deterministic BIST. The critical features of SSIC sequence are proposed for selecting seed vectors. The SSIC sequence generator is designed. The simulation results using benchmark circuits show that the SSIC sequences can increase fault coverage and decrease application time than random SIC sequences. SSIC sequence also has low dynamic power consumption.

This paper presents a simple yet efficient low hardware overhead testing scheme for scan-based built-in self-test (BIST) architecture that reduces switching activity (SA) in CUTs and test application time without compromising in the fault coverage. First demonstrated is the low transition LFSR (LT-LFSR) based test-per-scan scheme targeted for low heat dissipation during test by reducing the number of transitions at the cost of reduced fault coverage. Further explained is a proposed combined approach using both test-per-scan and test-per-clock application schemes, adding above LT-LFSR as the TPG and MISR for signature analysis. Experiments conducted on different ISCAS89 benchmark circuits shows that proposed scheme gives quite better fault coverage, that too, with a large reduction in test lengths and transitions (hence heat dissipation during testing)

We propose a new approach to the generation of compact test sets for scan circuits. Compaction refers here to a reduction in the test application time. The proposed procedure generates an initial test set that is likely to have a low test application time. It then applies an existing static compaction procedure to this initial test set to further compact it. As a by-product, the proposed procedure also results in long primary input sequences, which are applied at-speed. This contributes to the detection of delay defects. We demonstrate through experimental results the advantages of this approach over earlier ones as a method for generating test sets with minimal test application time and long primary input sequences.

Today, VLSI design has progressed to a stage where it needs to incorporate methods of testing circuits. The Automatic Test Pattern Generation (ATPG) is a very attractive method and feasible on almost any combinational and sequential circuit. Currently available automatic test pattern generators (ATPGs) generate test sets that may be excessively long. Because a cost of testing depends on the test length, compaction techniques have been used to reduce that length. The motivation for studying test compaction is twofold. Firstly, by reducing the test sequence length, the memory requirements during the test application and the test application time are reduced. Secondly, the extent of test compaction possible for deterministic test sequences indicates that test pattern generators spend a significant amount of time generating test vectors that are not necessary. The compacted test sequences provide a target for more efficient deterministic test generators. Two types of compaction techniques exist: dynamic and static. The dynamic test sequence compaction performs compaction concurrently with the test generation process and often requires modification of the test generator. The static test sequence compaction is done in a post-processing step to the test generation and is independent of the test generation algorithm and process. In the thesis, a new idea for static compaction of test sequences for synchronous sequential circuits has been proposed. Our new method - SUSEM (Set Up Sequence Elimination Method) uses the circuit state information to eliminate some setup sequences for the target faults and consequently reduce the test sequence length. The technique has been used for the test sequences generated by HITEC test generator. ISCAS89 benchmark circuits were used in our experiments, for some circuits which have a large number of target faults and relatively small number of flip-flops, the very significant compactions have been obtained. The more important is that this method can be used to improve the test generation procedure unlike most static compaction methods which blindly or randomly remove parts of test vectors and cannot be used to improve the test generators.

We present new methods to reduce test times in sequential circuits using scan. The problem of reducing test application time is shown to be computationally intractable. We discuss heuristic techniques to reduce test times. Fault simulation and correlation between test vectors are used to reduce test times, without affecting fault coverage. Our methods can be used to process a test set after test generation is complete. They lead to a substantial reduction in test times.

The restoration-based compaction procedures are the most computationally efficient static compaction procedures that reduce the length of a test sequence for a synchronous sequential circuit without reducing the fault coverage. We study one of the important components of the restoration-based compaction process, the initial omission process. This process selects test vectors that will be omitted from the test sequence initially, to start the restoration process. We also propose a specific procedure for the initial omission process. Experimental results for a variety of circuits and test sequences demonstrate that this procedure has a significant effect on the compacted test sequence length. Intuitively, the new procedure postpones the point at which the compaction procedure saturates, thus allowing smaller test lengths to be obtained before saturation is reached. The importance of continuing to explore this problem is related to the fact that static compaction procedures for synchronous sequential circuits are important for scan circuits as well.

In this paper, a novel compression/decompression test approach for system-on-a-chip (SoC) test using an embedded FPGA core is presented. The approach, employing Huffman coding, achieves test data volume and test application time reduction. The approach makes effective use of the embedded FPGA core such that the implementation is more efficient than that of the embedded processor-based approach. Due to the reconfigurable capability of FPGAs, the implementation of this approach has zero hardware overhead and higher flexibility in comparison with the general hardware-based implementation. Since the application with the FPGA has common problems of low speed and high power consumption, we demonstrate how to apply a CAM-based (content-addressable-memory) decompression architecture and low-power scan test vectors to overcome the difficulties. It is proven that the proposed approach is efficient from the experimental results.