Technology developments driving an evolution of cellular phone power amplifiers to integrated RF front-end modules

Millions of cellular phone power amplifiers (PA) are produced every day worldwide using a great diversity of technologies. This is true both for the active devices, where various silicon as well as GaAs transistors are being used, and for the PA design, in which MMIC, module and discrete solutions compete. This paper gives an overview of the various options for technological and architectural choices and their influence on PA performance, notably efficiency and linearity. It sketches the future of PA development towards more functional integration, which will be obtained by two paths: integration on chip and added functionality in modules.

Moving toward the third-generation (3G), wireless service providers (WSPs) have key decisions to make in evolving their backbone networks in a cost-effective way. Today, most WSPs in the United States deploy fully meshed, circuit-switched metro backbone networks and hand off long-distance traffic to an interexchange carrier (IXC). With the increased complexity of managing a growing meshed network and the emergence of enhanced data services, the goal is to evolve toward a multi-service packet network. This paper presents a rigorous model for circuit-to-packet (C2P) network evolution planning that addresses evolution alternatives for voice services, technology choice, network architectures, design, performance, reliability, and financial analysis. The model allows WSPs to quantify the benefits of various evolution scenarios and helps Lucent Mobility Solutions assess product roadmaps. The paper also presents a case study based on typical code division multiple access (CDMA) WSPs in North America that examines various C2P evolution strategies in metro, regional, and national backbones based on different choices of technology (TDM vs. ATM vs. IP), product availability, network architectures, and traffic forecasts. Also included are key insights and a summary of the study results.

In this paper, the recent advances of CDMA power amplifier module developments for wireless handset applications are reviewed. Technology choices among GaAs, SiGe and PHEMT for linear PA designs are compared. The trade-offs of circuit design and module approaches are discussed in detail. The measured performances of some representative state of the art power amplifier modules are presented. The high integration of more front-end components and functionalities into the power amplifier module and the increasing demand for high linear efficiency at lower output power has become a widely acceptable trend.

Comfort zone is an artificial mental boundary within which you maintain a sense of security. A couple of years ago, PRACE (Partnership for Advanced Computing in Europe) challenged the technology providers of Europe in proposing new architectures, new concepts and building a High-Performance Computer system mixing old and proven technology with advanced new components. E4 took the challenge and proposed an innovative and uncomfortable approach: DAVIDE. The talk will present the rationale for the technological and architectural choices done for building DAVIDE, the key innovative concepts, the software ecosystems and some preliminary performance.

To obtain high efficiency of dc to ac power conversion in an amplifier, it is necessary to decrease the power dissipation in the active device by ensuring that, the overlap of the voltage and current waveforms at the output terminals of the active device is minimized. This reduction of overlap is obtained by using load harmonic networks to shape the above waveforms at the output terminals of the active device. In the three common classes of high efficiency power amplifiers (PAs) (F. F-1 and E), this shaping is obtained by attenuating different harmonics of the waveforms by using load harmonic networks. For the class E amplifier a capacitance is placed across at the output terminals of the active device. This is to ensure that the output voltage is delayed until the active device is turned `off' and the output voltage reaches its minimum value with a slow turn `on'. If this device is driven hard 'on' and 'off' to obtain high efficiency it is shown that the input impedance must be very high at the harmonic frequencies. At the design frequency the required input impedance depends on the value of the above capacitance. Ideal lossless transmission lines (Tlines) are used in the initial design of harmonic networks for high efficiency power amplifiers and then practically realised using microstrip lines (Mlines). As the metal and substrate losses in Mlines are normally expressed in terms of attenuation constants, these losses are difficult determine as they require solutions of complex mathematical equations. In this paper to reduce such complex analysis the losses in an Mlines are modelled as a Tlines in series a resistance. A novel method is proposed to determine this resistance as a function of the length of the Mlines which is realised using inexpensive PCB FR4 substrate. Then for the above two line models, harmonic networks were designed up to the second harmonic and third harmonics and the obtained losses at the design frequency compared. Finally the effect of the losses by different harmonic networks on the class E amplifier is investigated.

The ultrasound instrumentation uses linear power amplifiers with low power efficiency, generating unwanted heat and resulting in the deterioration of the echo signal quality of measured targets. Therefore, this study aims to develop a power amplifier scheme to increase power efficiency while maintaining appropriate echo signal quality. In communication systems, the Doherty power amplifier has shown relatively good power efficiency while producing high signal distortion. The same design scheme cannot be directly applied to ultrasound instrumentation. Therefore, the Doherty power amplifier needs to be re-designed. To verify the feasibility of the instrumentation, a Doherty power amplifier was designed to obtain high power efficiency. The measured gain, output 1-dB compression point, and power-added efficiency of the designed Doherty power amplifier were 33.71 dB, 35.71 dBm, and 57.24% at 25 MHz, respectively. In addition, the performance of the developed amplifier was measured and tested using the ultrasound transducer through the pulse-echo responses. The output power with 25 MHz, 5-cycle, and 43.06 dBm generated from the Doherty power amplifier was sent through the expander to the focused ultrasound transducer with 25 MHz and 0.5″ diameter. The detected signal was sent via a limiter. Afterwards, the signal was amplified by a 36.8 dB gain preamplifier, and then displayed in the oscilloscope. The measured peak-to-peak amplitude in the pulse-echo response with an ultrasound transducer was 0.9698 V. The data showed a comparable echo signal amplitude. Therefore, the designed Doherty power amplifier can improve the power efficiency used for medical ultrasound instrumentation.

Technologies for fabrication of MEMS, optics and photonics at the micro- and nanoscale continue to advance and diversify due to rising demands for miniaturization, cost reduction, functional integration, and increased performance. Examples include diffractive optics, sub-wavelength optics, microrefractive optics, optical waveguides, photonic crystals, plasmonic devices, and heterogeneously integrated active and passive micro- and nano-optical devices. These devices are playing increasing roles in a wide range of applications, including sensors and actuators, communications, imaging, biomedical, data storage, and other areas. Both conventional and unconventional micro- and nanofabrication techniques serve as fundamental enablers for wide ranges of MEMS and passive and active optical components and devices.

The AMC&D program was formed in 1996 within PMA-209 to replace the AYK-14 within the F/A-18E/F. As the program has matured, other aircraft platforms, specifically AV-8B and T-45, have joined the effort. They will use portions of the AMC&D program hardware and software to meet their individual program needs. The reuse of these components was possible in part because of the During program definition, new requirements arose to replace cockpit displays that were experiencing DMS and would soon be unsupportable. The new displays will feature commercial high-resolution color digital displays modified for the military environment. Another addition to the program was a requirement to upgrade portions of the data bus. This upgrade brings a Fibre Channel network running on fiber-optic media to the F/A-18E/F. A key design feature of the program was to create a mission computer that could support a software environment that would dramatically reduce software maintenance costs. Recent flight-testing and software build efforts have shown that the program architecture and technology choices are on the right track to meet that key design goal.strict adherence to the system architecture, which includes an application program interface.

A description is given of the design, fabrication, and performance of the first reported monolithic voltage-controlled oscillator (VCO) using a heterojunction bipolar transistor (HBT) as the active device and an integrated p-n junction diode as the varactor. The monolithic VCO employs a self-aligned AlGaAs-GaAs HBT with ten emitter fingers (2.5 mu m*20 mu m each) whose maximum frequency of oscillation (f/sub max/) is 60 GHz. A continuous tuning bandwidth of 10.78-13.04 GHz (19%) was achieved with an output power of 219 mW and a DC-to-RF conversion efficiency of 31%. Maximum output power of 277 mW and 30% efficiency was also demonstrated at somewhat lower tuning bandwidths (11.00-11.88 GHz). The effects of bias voltage and current variations on the performance of the VCO have been studied. The single sideband FM noise of the free-running VCO was measured to be -55 dBc/Hz at 10 kHz offset and -75 dBc/Hz at 100 kHz offset from the carrier (11.26 GHz). These results indicate that HBT can be a viable broadband microwave source for high-power, low-phase-noise system applications. >

RECENT progress in wide bandgap power (WBG) switches shows great potential. Silicon carbide (SiC) is a promising material for power devices with breakdown voltages of several hundred volts up to 10 kV. SiC Schottky power diodes have achieved widespread commercial acceptance. Recently, much progress has been made on active SiC switches, including JFETs, thyristors, BJTs, IGBTs, and MOSFETs. Many a great promise has been made, and wondrous claims abound, but the question remains: will they live up to the hype? We explore this question for the class of high-frequency, hard-switched converters with input voltages of up to 600 VDC and power throughputs in the kilowatt range. Experimental evidence shows that both superior efficiency and higher power density may be obtained via the use of SiC MOSFETs. A direct comparison is made using silicon power devices (IGBTs and MOSFETs) and SiC MOSFETs in a 200 kHz, 6 kW, 600 V hard-switched converter. The losses are measured and conduction and switching losses of the active devices are estimated. Total losses can be reduced by a factor of 2-5 by substitution of SiC MOSFETs for Si active power devices.

Orthogonal Frequency Division Multiplexing (OFDM) suffers from a high Peak-to-Average Power Ratio (PAPR). Designing a High Power Amplifier (HPA) with high PAPR is not a wise technique as it roots the amplifier to operate in a non-linear region which is intricate. Linearity and power efficiency are important constraints of HPA which cannot be achieved at the same time. Therefore, perfect linearity is observed when efficiency is low or vice versa and efficiency can be improved by decreasing the PAPR. In this paper, the PAPR is mitigated by using Partial Transmit Sequence (PTS), Selected Mapping (SLM), Hybrid and proposed methods. Analysis of OFDM with high PAPR passing through different HPA models is evaluated in terms of Power Spectral Density (PSD), gain and efficiency for all PAPR reduction methods considered in this work. The results are encouraging by using hybrid PAPR reduction method, HPAs can be operated in a linear region to provide higher efficiency compared to non-hybrid PAPR reduction methods. Hence, hybrid PAPR reduction methods can be used even in future wireless communications systems including 5G and beyond.

Nowadays transducers are ubiquitous as interfaces between the increasingly digital world and the real physical world. The same holds for the power amplifiers driving them. This thesis focuses on the design and optimization of high-voltage class-D amplifiers, which are used for driving capacitive piezoelectric actuator loads in active vibration/noise control applications. The main objective is to further enhance class-D power efficiency compared to existing class-D designs. To gain insight in class D power efficiency, a detailed analysis of high-voltage class-D dissipation sources is performed and a dissipation model including all the major dissipation sources is developed. The analysis shows that switching loss is a potential dominating dissipation source in high-voltage applications, while its contribution can be minimized by fast switching to eliminate V-I overlap losses. Moreover, it is shown that when varying the class-D switching frequency, a minimum total dissipation exists, with the optimal switching frequency depending on the output power. Furthermore, idle loss reduction by increasing the switching frequency and inserting a dead time to the power stage is backed by the analysis. Following the analysis, a fast-switching power stage is designed to aim for switching loss minimization. This output stage design features immunity to the on-chip supply bounce, realized by internally regulated floating supplies, variable driving strength for the gate driver, and an efficient 2-step level shifter design. Fast switching transitions and low switching loss are achieved with 94% peak efficiency for the complete class-D power stage in the realized chip. In addition, gate driver sizing procedures for the class-D output stage are discussed, showing that the variable gate driving strength can greatly improve efficiency when on-chip supply bounce is the limiting factor. Also based on the dissipation analysis, this thesis describes the design of an efficiency-improved high-voltage class-D power amplifier. The amplifier adaptively regulates its switching frequency for optimal power efficiency across the full output power range. This is based on detecting the switching output node voltage level at the turn-on transition of the power switches. For the final chip prototype, the amplifier achieves 93% efficiency at 45W output power, >80% power efficiency down to 4.5W output power and >49% efficiency down to 0.45W output power. Finally, for the aim of idle loss reduction, the linearity degradation of dead time insertion and switching frequency increase is discussed in this thesis. To cope with this linearity degradation, both open-loop and closed-loop error correction techniques are explored and it is further shown that a higher-order loop filter combined with uniform sampling once per switching cycle is potentially a suitable choice for closed-loop fixed-carrier class-D implementations.

Large antenna arrays at the base station can facilitate power efficient single user downlink communication due to the inherent array power gain, i.e., under an average only total transmit power constraint, for a fixed desired information rate, the required total transmit power can be reduced by increasing the number of base station antennas (e.g. with i.i.d. fading, the required total transmit power can be reduced by roughly 3 dB with every doubling in the number of base station antennas, i.e., an O(N) array power gain can be achieved with N antennas). However, in practice, building power efficient large antenna arrays would require power efficient amplifiers/analog RF components. With current technology, highly linear power amplifiers generally have low power efficiency, and therefore linearity constraints on power amplifiers must be relaxed. Under such relaxed linearity constraints, the transmit signal that suffers the least distortion is a signal with constant envelope (CE). In this paper, we consider a single user Gaussian multiple-input single-output (MISO) downlink channel where the signal transmitted from each antenna is constrained to have a constant envelope (i.e., for every channel-use the amplitude of the signal transmitted from each antenna is constant, irrespective of the channel realization). We show that under such a per-antenna CE constraint, the complex noise-free received signal lies in the interior of a “doughnut” shaped region in the complex plane. The per-antenna CE constrained MISO channel is therefore equivalent to a doughnut channel, i.e., a single-input single-output (SISO) AWGN channel where the channel input is constrained to lie inside a “doughnut” shaped region. Using this equivalence, we analytically compute a closed-form expression for an achievable information rate under the per-antenna CE constraint. We then show that, for a broad class of fading channels (i.i.d. and direct-line-of-sight (DLOS)), even under the more stringent per-antenna CE constraint (compared to the average only total power constraint), an O(N) array power gain can still be achieved with N base station antennas. We also show that with N ≫1, compared to the average only total transmit power constrained channel, the extra total transmit power required under the per-antenna CE constraint, to achieve a desired information rate is small and bounded for a broad class of fading channels (i.i.d. and DLOS). We also propose novel CE precoding algorithms. The analysis and algorithms presented are general and therefore applicable to conventional systems with a small number of antennas. Analytical results are supported with numerical results for the i.i.d. Rayleigh fading channel.

This paper presents a 1.9 GHz linear power amplifier (PA) architecture that improves its power efficiency in the power back-off (PBO) region. The combination of power transistor segmentation and digital gain compensation effectively enhances its power efficiency. A fast switching scheme is proposed, such that PA segments are switched on and off according to signal power, i.e. the proposed scheme makes the PA power consumption correlate with the power of the input signal. Binary power gain variations due to segmentation are dynamically compensated in the digital domain. The proposed solution overcomes the trade-off between efficiency and linearity by employing the digital predistortion technique. The PA is implemented in 40 nm CMOS process, it delivers a saturated output power of 35 dBm with 44.9% power-added efficiency (PAE) and linear gain of 38 dB. The adjacent channel leakage ratio (ACLR) at ±5 MHz at a maximum linear output power of 31 dBm for a baseband WCDMA signal is -35.8 dBc.

The design of a new high-efficiency switching power amplifier with an ultralow-power spread spectrum clock generator (SSCG) is first reported in this paper. An effective low-power frequency modulation method is first proposed to reduce the electromagnetic interference of the pulse width modulation class D power amplifier without degrading its power efficiency. Also, a simple <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</i> voltage feedback circuit is used to reduce the total harmonic distortion (THD). This amplifier proves to be a cost-effective solution for designing high fidelity and high efficiency audio power amplifiers for portable applications. Measurement results show that the power efficiency and THD can reach 90% and 0.05%, respectively. The power dissipation of the SSCG is only 112 ¿W. The harmonic peaks of the switching frequency are greatly reduced when the SSCG technique is applied to the amplifier design. The impact of the SSCG on the THD of the class D power amplifier is also first reported in this paper. This switching power amplifier is implemented using a Taiwan Semiconductor Manufacture Company (TSMC) 0.35- ¿m CMOS process.