Testing high speed VLSI devices using slower testers

Today, VLSI design has progressed to a stage where it needs to incorporate methods of testing circuits. The Automatic Test Pattern Generation (ATPG) is a very attractive method and feasible on almost any combinational and sequential circuit. Currently available automatic test pattern generators (ATPGs) generate test sets that may be excessively long. Because a cost of testing depends on the test length, compaction techniques have been used to reduce that length. The motivation for studying test compaction is twofold. Firstly, by reducing the test sequence length, the memory requirements during the test application and the test application time are reduced. Secondly, the extent of test compaction possible for deterministic test sequences indicates that test pattern generators spend a significant amount of time generating test vectors that are not necessary. The compacted test sequences provide a target for more efficient deterministic test generators. Two types of compaction techniques exist: dynamic and static. The dynamic test sequence compaction performs compaction concurrently with the test generation process and often requires modification of the test generator. The static test sequence compaction is done in a post-processing step to the test generation and is independent of the test generation algorithm and process. In the thesis, a new idea for static compaction of test sequences for synchronous sequential circuits has been proposed. Our new method - SUSEM (Set Up Sequence Elimination Method) uses the circuit state information to eliminate some setup sequences for the target faults and consequently reduce the test sequence length. The technique has been used for the test sequences generated by HITEC test generator. ISCAS89 benchmark circuits were used in our experiments, for some circuits which have a large number of target faults and relatively small number of flip-flops, the very significant compactions have been obtained. The more important is that this method can be used to improve the test generation procedure unlike most static compaction methods which blindly or randomly remove parts of test vectors and cannot be used to improve the test generators.

Short test sequences for synchronous sequential circuits are important in reducing test application time and memory requirements. In addition, dynamic test compaction, where heuristics to generate short test sequences are incorporated into the test generation process, may also reduce test generation time. This is due to the fact that a smaller number of test vectors needs to be generated. We present a dynamic test compaction procedure. The compaction heuristics we use are based on previously proposed static compaction techniques. Conventionally, static compaction is applied as a postprocessing step, after the test sequence has been generated. In the proposed procedure, static compaction techniques are used while the test sequence is being generated, to reduce the need for postprocessing, or static compaction. Compared to other dynamic compaction procedures that generate very short test sequences, the computational overhead involved in the proposed procedure is significantly lower, yet short test sequences are obtained. The proposed techniques can be incorporated into other test generation procedures, to reduce the test lengths they produce.

<p>Test generation procedures for large VLSI designs are required to achieve close to 100% fault coverage using a small number of tests. They also must accommodate on-chip test compression circuits which are widely used in modern designs. To obtain test sets with small sizes one could use extra hardware such as test points or use software techniques. An important aspects impacting test generation is the number of specified positions, which facilitate the encoding of test cubes when using test compression logic. Fortuitous detection or generation of tests such that they facilitate detection of yet not targeted faults, is also an important goal for test generation procedures.</p> <p>At first, we consider the generation of compact test sets for designs using on-chip test compression logic. We introduce two new measures to guide automatic test generation procedures (ATPGs) to balance between these two contradictory requirements of fortuitous detection and number of specifications. One of the new measures is meant to facilitate detection of yet undetected faults, and the value of the measures is periodically updated. The second measure reduces the number of specified positions, which is crucial when using high compression. Additionally, we introduce a way to randomly choose between the two measures.</p> <p>We also propose an ATPG methodology tailored for BIST ready designs with X-bounding logic and test points. X-bounding and test points used to have a significant impact on test data compression by reducing the number of specified positions. We propose a new ATPG guidance mechanism that balances between reduced specifications in BIST ready designs, and also facilitates detection of undetected faults. We also found that compact test generation for BIST ready designs is influenced by the order in which faults are targeted, and we proposed a new fault ordering technique based on fault location in a FFR. Transition faults are difficult to test and often result in longer test lengths, we propose a new fault ordering technique based on test enumeration, this ordering technique and a new guidance approach was also proposed for transition faults. Test set sizes were reduced significantly for both stuck-at and transition fault models.</p> <p>In addition to reducing data volume, test time, and test pin counts, the test compression schemes have been used successfully to limit test power dissipation. Indisputably, toggling of scan cells in scan chains that are universally used to facilitate testing of industrial designs can consume much more power than a circuit is rated for. Balancing test set sizes against the power consumption in a given design is therefore a challenge. We propose a new Design for Test (DFT) scheme that deploys an on-chip power-aware test data decompressor, the corresponding test cube encoding method, and a compression-constrained ATPG that allows loading scan chains with patterns having low transition counts, while encoding a significant number of specified bits produced</p> <p>by ATPG in a compression-friendly manner. Moreover, the new scheme avoids periods of elevated toggling in scan chains and reduces scan unload switching activity due to unique test stimuli produced by the new technique, leading to a significantly reduced power envelope for the entire circuit under test.</p>

This paper presents a nonscan design-for-testability (DFT) method for register-transfer-level (RTL) circuits. We first introduce the notation to analyze the test generation complexity, as well as two classes of sequential circuits, namely: 1) the combinationally testable class and 2) the acyclically testable class. Then, we introduce a new class of linear-depth time-bounded circuits as one of the acyclically testable classes. The linear-depth time-bounded testability guarantees that the number of time frames required for any testable fault is bounded by a linear function of the number of flip-flops in the circuit during the test generation process. As one of the linear-depth time-bounded classes, we introduce a new class of RTL circuits, called the cycle-unrollable RTL circuits, which is shown to be linear depth time bounded. We propose a DFT method to make RTL circuits cycle unrollable and a test generation method for cycle-unrollable RTL circuits. Experimental results show that we can drastically reduce hardware overhead and test application time compared to the full-scan method and the method proposed by Ohtake Moreover, our proposed method can achieve 100% fault efficiency for gate-level single stuck-at faults in practical test generation time and allow at-speed testing.

Methods to test sequential circuits for delay faults are discussed. A method called at-speed testing is proposed for simplifying test application and reducing test length. A value system to allow at-speed testing is developed, and a test generation procedure is presented. The effect of at-speed test application on the path delay fault model is described. Experimental results are presented, demonstrating the applicability of at-speed testing and its effect on test length. >

We propose three static compaction techniques for test sequences of synchronous sequential circuits. We apply the proposed techniques to test sequences generated for benchmark circuits by various test generation procedures. The results show that the test sequences generated by all the test generation procedures considered can be significantly compacted. The compacted sequences thus have shorter test application times and smaller memory requirements. As a by product, the fault coverage is sometimes increased as well. More importantly, the ability to significantly reduce the length of the test sequences indicates that it may be possible to reduce test generation time if superfluous input vectors are not generated.

A method for generating tests for gate-level stuck-at faults in sequential machines is given, which is applicable when a state-table description of the machine under test is either given or extractable from the given description. A test generation procedure for faults in the state table is first described. The test generation procedure is polynomial in the size of the state table, and is complete and accurate in the following sense. For every given state-table fault, the procedure provides either a minimum-length test, or a proof that the fault is undetectable. This test generation procedure is used for generating complete test sets for stuck-at faults in a gate level implementation of the machine, by translating stuck-at faults in the gate-level implementation into faults in the state table. The translation includes modeling and extraction. Modeling consists of a simple method to select a small subset of state-table faults such that a test set for these faults yields very high coverage of stuck-at faults in the actual implementation. Extraction consists of accurate translation of stuck-at faults in the implementation into equivalent state-table faults, and can be used to derive tests for stuck-at faults which are not detected by the test set for the modeled faults. Based on the test generation algorithm developed and the modeling and extraction of stuck-at faults to translate them into state-table faults, a method to achieve 100% fault-efficiency for stuck-at faults is proposed, and experimental results for stuck-at faults are presented. Short test sequences are shown to be obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A typical VLSI design flow is iterative, implying that performance, power, area and testability are improved iteratively. With the shift left paradigm, most of the changes made to a design, including to a large extent changes to address testability, occur at the RTL. Test generation is an exception with a gate level netlist being required by ATPG tools. Within an iterative flow, repeated ATPG to reevaluate the testability of a design after its RTL has been changed becomes a bottleneck. To address this bottleneck, the test generation process needs to transform a test set generated for an earlier version of the design into a test set for a new version without repeating the entire test generation process. To enable the transformation, it is necessary to find a mapping between the inputs and outputs of the earlier and new versions of the design. The main contribution of the paper is to compute such a mapping after RTL changes and resynthesis produce a new gate level netlist, where signal names may have changed, new signals may have been introduced, and signals that existed earlier may have been removed. Experimental results for industrial circuits with changes made at the RTL show an average of 5-fold reduction in test generation time.

Hardware testing is a process aimed at detecting manufacturing faults in integrated circuits. To measure test quality, two main metrics are in use: fault detection abilities (fault coverage) and test application time (test length). Many algorithms have been suggested for test generation; however, no scalable solution exists. In this paper, we analyze applicability of functional tests generated from high-level models for low-level manufacturing testing. A particular test generation method is considered. The input information is an HDL description. The key steps of the method are system model construction and coverage model construction. Both models are automatically extracted from the given description. The system model is a representation of the design in the form of high-level decision diagrams. The coverage model is a set of LTL formulae defining reachability conditions for the transitions of the extended finite state machine. The models are translated into the input format of a model checker. For each coverage model formula the model checker generates a counterexample, i.e. an execution that violates the formula (makes the corresponding transition to fire). The approach is intended for covering of all possible execution paths of the input HDL description and detecting dead code. Experimental comparison with the existing analogues has shown that it produces shorter tests, but they achieve lower stuck-at fault coverage comparing with the dedicated approach. An improvement has been proposed to overcome the issue.

SAT-based generation of compressed skewed-load tests for transition delay faults

Three issues that are dominating test research today are test application time, test data volume and test power. Researchers have focused on these issues mostly considering the popular serial scan architecture for its relatively low hardware overhead while ignoring the fact that exponential drop in hardware cost offers opportunities for implementing a test architecture that previously may have been unacceptable. This paper takes such a paradigm shift into account and studies the simultaneous solution of all three problems of serial scan by making use of progressive random access scan test architecture. This architecture only increases the hardware cost marginally while providing marked improvements for the three issues. This paper explains the test architecture and then develops a test generation methodology which reduces the test application time by nearly 75%, test data volume by 50% for the benchmark circuits. Above all, the architecture is inherently so efficient that it reduces the test power by nearly 99% or more of the test power consumption compared to serial scan

To reduce total chip production costs, circuits must be more testable. Several design for testability schemes which tradeoff various design parameters have been proposed toward that end. The recently proposed partial reset (PR) method is incorporated. Rather than allowing all memory elements in a sequential circuit to be reset by a primary input, only a subset of them is given the capability to reset. PR has less hardware overhead and typically smaller test application times than scan design, PR, furthermore, allows unrestricted at-speed testing. The tradeoff is in slightly lower testability. A dynamic PR flip flop selection method is described utilizing a fast sequential test generator. The automated system developed in this research works closely with the test generator to insert PR, observability enhancements and partial scan into a given circuit. The result is higher fault coverage than is possible with PR alone and faster test application times than scan design. Results are shown on all ISCAS'89 circuits, up to s9234. Even though multiple runs of test generation is performed, CPU times are comparable to a single run of conventional deterministic automatic test pattern generations.

Efficient test generation methods and design-for-testability schemes are critical to ensure the quality of multimedia cores. By investigating the potential test problems existing in these cores, This work presents a series of efficient test methods to significantly reduce the test application time for these cores while obtaining 100% fault coverage. The test development procedure is demonstrated by employing a well-known 2-D discrete cosine transform (DCT) circuit that is implemented in the typical row-column decomposition method. The 100% fault coverage is first achieved by appropriately modifying the original design, including scan design insertion and some ad hoc revisions. We then apply the recently-developed input reduction method and the broadcasting scan method to overcome the deficiency of long test application time when inserting scan design into the circuits. With these two methods, the test application time can be reduced to 6.8% of those required by the single full scan designs, while only 7.9% area overhead is needed.

The authors define the notion of a lingering synchronisation effect. Such an effect occurs when a primary input cube (an incompletely specified primary input vector) determines the state of a circuit for several time units after it is applied. A primary input cube with a lingering synchronisation effect may prevent certain faults from being detected when it appears repeatedly in a test sequence. It should therefore be avoided when the goal is to achieve a high fault coverage. The authors demonstrate that benchmark circuits have primary input cubes with small numbers of specified values (typically one or two), which have lingering synchronisation effects. In some cases, the synchronisation effects linger for large numbers of time units. The authors define a ranking of primary input cubes based on the severity of their lingering synchronisation effects. They describe a random test generation process that avoids primary input cubes with lingering synchronisation effects, and achieves high fault coverage for benchmark circuits. The test generation process uses the severity of the lingering synchronisation effects of the primary input cubes to decide on the ones it should avoid.

A test scheme for crosstalk faults, based on an oscillation signal, is proposed. It uses an oscillation signal applied to an affecting line and detects induced pulses on a victim line if a crosstalk fault exists between these two lines. It is simple and eliminates the complicated timing issues during test generation for crosstalk faults in conventional approaches. The test generation and fault simulation based on the scheme are described. Experimental results are also presented to show the described test generation procedure is effective in generating test patterns for this scheme.