TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction

Having presented fabrication technology for IC chips in Chap. 2, we now investigate in detail an important aspect of the physical design process: data interfaces. We introduce circuit, layout and mask data structures, that is, the main input and output data in the design steps, in this chapter. First, we explain the input to physical design—circuit data—while focusing on schematics and netlists (Sect. 3.1); we then discuss the output of the physical design step: layout data such as layers and polygons (Sect. 3.2). Mask data, which are the data required by the foundry and generated at the end of the design process, are described in Sect. 3.3. Here, we introduce “layout post processing”, where amendments and additions to the chip layout data are performed in order to convert a physical layout into data for mask production. Technology data, provided by the chip manufacturing foundry, are crucial for producing the physical design. An important portion of these data are technological constraints which are modeled in the geometrical design rules used in physical design. Essentially, geometrical design rules are constraints for physical design, whose compliance ensures the manufacturability of the layout results. Geometrical design rules are presented in detail in Sect. 3.4. Technology data are organized in libraries. These libraries, which are extensively used in IC and PCB design, are covered in our final Sect. 3.5.

Coupling Of Synthesis And Layout: Challenges And Solutions

Extending classical functional dependencies for physical database design

Placement is a step in the physical design associated with laying the cells of an integrated circuit in a designated area, so that timing, congestion, and utilization goals are met. Placement is a major step in physical design thus, applying optimization methods relies heavily on implementing processes from scratch or the reuse of code that has been previously tested in similar procedures. A modern placer needs to handle large amount of cells with different sizes and placement constraints. For both industry and academia, a toolset comprising widely used functionalities, can be extremely practical and reduce the development and testing cycle. In this paper we present the Bookshelf Format Parser, a management toolset for bookshelf formatted designs, accompanied by an extensive evaluation of its elaborate and versatile architecture. We evaluate the performance of the proposed toolset using benchmarks derived from actual designs. Numerical results depict the performance of the proposed approach in terms of execution time and memory consumption while a comparative assessment reveals the position of the paper in the relevant literature.

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In Chap. 2 we covered technologies and in Chap. 3 we saw how these technologies interface with physical design. Here in Chap. 4 we now provide an end-to-end overview of the physical design process, namely how to physically construct the layout of an electronic circuit. In this chapter we present the fundamental knowledge an engineer must possess to carry out this task. In Chap. 5 we then discuss each of the specific physical design steps in further detail. We begin the chapter by introducing the design flow (Sect. 4.1), design models (Sect. 4.2) and design styles (Sect. 4.3). Next, we investigate various design tasks and related tools (Sect. 4.4), before discussing optimization goals and design constraints (Sect. 4.5). Up to this point our treatise has focused mainly on the digital design flow. In Sect. 4.6 we introduce the characteristics of, and differences between, analog, digital, and mixed-signal design flows. Looking toward the future, we conclude the chapter by presenting two different yet complementary visions for analog-design automation to overcome the analog-digital design gap (Sect. 4.7).

Circuit Partitioning generally formulated as graph partitioning problem is an important step in physical design of circuits. The use of Evolutionary techniques is increasingly used to solve NP complete problems i.e. Applications for logic minimization and simulation heuristics. This paper explores the evolutionary approach of genetic algorithm and propose a hybrid technique involving the strengths of the existing techniques resulting in a better partitioning and placement of circuits. It can further be extended to the Hardware/Software boundary of algorithms and can be applied to real world physical design problems.

First steps of the overall integration design of CFETR

Studio-based learning (SBL), the centerpiece of architecture and fine arts education for over a century, has become increasingly attractive to computing educators. SBL can be conceptualized as an iterative process of solution refinement that relies heavily on shared physical space and design critiques. This session will explore ways in which CS educators can transition aspects of traditional or face-to-face SBL to an online learning environment. We will discuss the potential for online studios, how they might look and function, and how their effectiveness in promoting student learning might be gauged. As more and more CS courses assume an online presence, we seek to understand both the opportunities and the limitations associated with conducting critical studio work in a digital medium.

Floorplanning is a crucial process in the early stage of VLSI physical design. It determines the performance, reliability, and size of chips. B*-tree is a simple yet efficient representation that encodes the layout of modules in a compact and non-slicing structure. Several B*-tree variants and corresponding operators have been proposed to deal with non-slicing floorplanning. However, these operators are considered and applied individually. A collective manipulation of them remains missing. This study proposes a genetic algorithm (GA) that enables multiple crossover and mutation operators for solving the non-slicing floorplanning problem. In particular, the GA selects one crossover operator and one mutation operator from the pool of operators whenever reproducing an offspring. The probability for an operator to be selected is based on its empirical performance. This study conducts experiments on two well-known benchmarks to examine the effectiveness of the proposed method. The experimental results show that the GA can achieve superior solution quality and efficiency on the non-slicing VLSI floorplanning.

Online image search result grouping with MapReduce-based image clustering and graph construction for large-scale photos

Circuit placement is a very important step in the physical VLSI circuit design, since it has a pronounced affect on the final chip layout. In this paper, a new neural network based on Kohonen's self-organization algorithm is introduced to solve the placement of arbitrarily sized cells in an arbitrarily shaped region. Experimental results show that the proposed method is better than the previous. >

Flow-based microfluidic biochips are attracting increasing attention with successful applications in lab-on-a-chip experiments and point-of-care diagnosis. Physical design for flow-based biochips determines the number of flow-channel intersections, and thus affects the number of microvalves. As reducing microvalves will significantly improve the overall design quality and reliability, physical design is of great importance. Typically, physical design consists of two major stages, i.e., component placement and routing. Existing works follow the step-by-step scheme, which perform placement and routing separately. The lack of interactions between the two design stages results in degraded design with large number of unfavorable channel intersections and microvalves. This paper presents a novel placement and routing method based on the sequence-pair representation, which seamlessly integrates placement and routing stages and allows iterative placement adjustment upon routing feedbacks. Experimental results show that compared with the existing work, the proposed method obtains average 54.10% improvement in flow-channel crossings, 42.15% improvement in total chip area, and 23.43% improvement in total channel length.

To address the problem that the two phases of flow-level physical design, i.e., component placement and routing, are usually considered separately and their interaction is neglected, resulting in the degradation of design quality and biochip execution efficiency, an effective sequence-pair-based flow-level physical design algorithm for continuous-flow microfluidic biochips is proposed. Firstly, based on the sequence-pair representation method which can quickly enumerate and calculate the placement solution, the component placement solution is obtained by the discrete particle swarm optimization algorithm with higher solving efficiency to further improve the quality of the placement solution. Then, the Manhattan distance between component pairs is considered as the basis for routing order in the routing stage, and the routing is performed by the negotiation-based routing algorithm to effectively reduce the number of crossings in the flow channel. Finally, the interaction between placement and routing is considered, and the placement is adjusted according to the feedback information of routing, thus bridging the component placement and routing phases. The benchmark test set of actual biochemical application reaction and synthesis is adopted, and the flow-level physical design algorithm based on simulated annealing placement and negotiated routing is reproduced as the comparison algorithm for the experiment. The experimental results show that the proposed algorithm optimizes the number of flow path intersections by 74.94%, the chip area by 5.04%, and the total flow path length by 16.88%, resulting in a high-quality flow path physical design solution.

With the increasing number of embedded memories in the modern system-on-chips (SOCs), the cost of memory testing becomes significant. Built-in-self-test (BIST) is an effective technique for memory testing. However, BIST has a negative impact on physical design (e.g., area and routing). Moreover, the grouping and placement of memory BIST controllers also greatly influences the test application time. In this paper, we propose an integer linear programming (ILP) approach to optimize the memory BIST design with both physical design (grouping and placement of memory BIST controllers) and test application time considered. Experimental results consistently show that our approach works well in practice.