Tolerant Locally Testable Codes

A q-query locally testable code (LTC) is an error correcting code that can be tested by a randomized algorithm that reads at most q symbols from the given word. An important question is whether there exist LTCs that have the c 3 property: constant rate, constant relative distance, and that can be tested with a constant number of queries. Such LTCs are sometimes referred to as “asymptotically good”.We show that dense LTCs cannot be c 3. The density of a tester is roughly the average number of distinct local views in which a coordinate participates. An LTC is dense if it has a tester with density ω(1).More precisely, we show that a 3-query locally testable code with a tester of density ω(1) cannot be c 3. Furthermore, we show that a q-locally testable code (q > 3) with a tester of density ω(1)n q − 2 cannot be c 3. Our results hold when the tester has the following two properties: (no weights:) Every q-tuple of queries occurs with the same probability. (‘last-one-fixed’:) In every q-query ‘test’ of the tester, the value to any q − 1 of the symbols determines the value of the last symbol. (Linear codes have constraints of this type). We also show that several natural ways to quantitatively improve our results would already resolve the general c 3 question, i.e. also for non-dense LTCs.

Locally testable codes (LTCs) of constant minimum (absolute) distance that allow the tester to make a nearly linear number of queries have become the focus of attention recently, due to their connections to central questions in approximability theory. In particular, the binary Reed-Muller code of block length N and absolute distance d is known to be testable with O(N/d) queries, and has a dimension of a N − (log N)log d. The polylogarithmically small co-dimension is the basis of constructions of small set expanders with many bad eigenvalues, and size-efficient PCPs based on a shorter version of the long code. The smallest possible co-dimension for a distance d code (without any testability requirement) is a d/2 log N, achieved by BCH codes. This raises the natural question of understanding where in the spectrum between the two classical families, Reed-Muller and BCH, the optimal co-dimension of a distance d LTC lies --- in other words the price one has to pay for local testability.One promising approach for constructing LTCs is to focus on affine-invariant codes, whose structure makes testing guarantees easier to deduce than for general codes. Along these lines, the authors of [HRZS13] and [GKS13] recently constructed an affine-invariant family of high-rate LTCs with slightly smaller co-dimension than Reed-Muller codes. In this work, we show that their construction is essentially optimal among linear affine-invariant LTCs that contain the Reed-Muller code of the appropriate degree.

We continue the study of the trade‐off between the length of probabilistically checkable proofs (PCPs) and their query complexity, establishing the following main results (which refer to proofs of satisfiability of circuits of size n): 1. We present PCPs of length $\exp(o(\log\log n)^2)\cdot n$ that can be verified by making $o(\log\log n)$ Boolean queries. 2. For every \epsilon>0, we present PCPs of length $\exp(\log^\epsilon n)\cdot n$ that can be verified by making a constant number of Boolean queries. In both cases, false assertions are rejected with constant probability (which may be set to be arbitrarily close to 1). The multiplicative overhead on the length of the proof, introduced by transforming a proof into a probabilistically checkable one, is just quasi polylogarithmic in the first case (of query complexity $o(\log\log n)$), and is $2^{(\log n)^\epsilon}$, for any $\epsilon > 0$, in the second case (of constant query complexity). Our techniques include the introduction of a new variant of PCPs that we call “robust PCPs of proximity.” These new PCPs facilitate proof composition, which is a central ingredient in the construction of PCP systems. (A related notion and its composition properties were discovered independently by Dinur and Reingold.) Our main technical contribution is a construction of a “length‐efficient” robust PCP of proximity. While the new construction uses many of the standard techniques used in PCP constructions, it does differ from previous constructions in fundamental ways, and in particular does not use the “parallelization” step of Arora et al. [J. ACM, 45 (1998), pp. 501–555]. The alternative approach may be of independent interest. We also obtain analogous quantitative results for locally testable codes. In addition, we introduce a relaxed notion of locally decodable codes and present such codes mapping k information bits to codewords of length $k^{1+\epsilon}$ for any $\epsilon>0$.

Article Free Access Share on Probabilistically checkable proofs with zero knowledge Authors: Joe Kilian NEC Research Institute NEC Research InstituteView Profile , Erez Petrank DIMACS Center, P.O.Box 1179, Piscataway, NJ DIMACS Center, P.O.Box 1179, Piscataway, NJView Profile , Gábor Tardos Mathematical Institute of the Hungarian Academy of Sciences, Pf. 127, Budapest, H-1364 Hungary and Institute for Advanced Study, Princeton, NJ Mathematical Institute of the Hungarian Academy of Sciences, Pf. 127, Budapest, H-1364 Hungary and Institute for Advanced Study, Princeton, NJView Profile Authors Info & Claims STOC '97: Proceedings of the twenty-ninth annual ACM symposium on Theory of computingMay 1997 Pages 496–505https://doi.org/10.1145/258533.258643Online:04 May 1997Publication History 24citation435DownloadsMetricsTotal Citations24Total Downloads435Last 12 Months34Last 6 weeks3 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

Error correction codes (ECCs) are commonly used in computer systems to protect information from errors. For example, single error correction (SEC) codes are frequently used for memory protection. Due to continuous technology scaling, soft errors on registers have become a major concern, and ECCs are required to protect them. Nevertheless, using an ECC increases delay, area and power consumption. In this way, ECCs are traditionally designed focusing on minimizing the number of redundant bits added. This is important in memories, as these bits are added to each word in the whole memory. However, this fact is less important in registers, where minimizing the encoding and decoding delay can be more interesting. This paper proposes a method to develop codes with 1-gate delay encoders and 4-gate delay decoders, independently of the word length. These codes have been designed to correct single errors only in data bits to reduce the overhead.

The PCP (i.e., Probabilistically Checkable Proofs) Theorem [8, 7, 22, 5, 4] states that any mathematical proof can be converted to a format that can be checked by a veri er making only a constant number of queries to the proof. The veri er picks the queries in a randomized way and might err with low probability.

The "direct-product code" of a function $f$ gives its values on all $k$-tuples $(f(x_1),\dots, f(x_k))$. This basic construct underlies "hardness amplification" in cryptography, circuit complexity, and probabilistically checkable proofs (PCPs). Goldreich and Safra [SIAM J. Comput., 29 (2000), pp. 1132--1154] pioneered its local testing and its PCP application. A recent result by Dinur and Goldenberg [Proceedings of the Forty-Ninth Annual IEEE Symposium on Foundations of Computer Science, 2008, pp. 613--622] enabled for the first time testing proximity to this important code in the "list-decoding" regime. In particular, they give a $2$-query test which works for polynomially small success probability $1/k^{\alpha}$ and show that no such test works below success probability $1/k$. Our main result is a $3$-query test which works for exponentially small success probability $\exp({-k^{\alpha}})$. Our techniques (based on recent simplified decoding algorithms for the same code [R. Impagliazzo et al., Proceedings of the Fortieth Annual ACM Symposium on Theory of Computing, 2008, pp. 579--588]) also allow us to considerably simplify the analysis of the 2-query test of [Proceedings of the Forty-Ninth Annual IEEE Symposium on Foundations of Computer Science, 2008, pp. 613--622]. We then show how to derandomize their test, achieving a code of polynomial rate, independent of $k$, and success probability $1/k^{\alpha}$. Finally, we show the applicability of the new tests to PCPs. Starting with a 2-query PCP with a projection property over an alphabet $\Sigma$ and with soundness error $1-\delta$, Rao [Proceedings of the Fortieth Annual ACM Symposium on Theory of Computing, 2008, pp. 1--10] (building on Raz's ($k$-fold) parallel repetition theorem [R. Raz, SIAM J. Comput., 27 (1998), pp. 763--803] and Holenstein's proof [T. Holenstein, Proceedings of the Thirty-Ninth Annual ACM Symposium on Theory of Computing, 2007, pp. 411--419] obtains a new 2-query PCP over the alphabet $\Sigma^k$ with soundness error $\exp(-\delta^2 k)$. Our techniques yield a 2-query PCP with soundness error $\exp(-\delta \sqrt{k})$. Our PCP construction turns out to be essentially the same as the miss-match proof system defined and analyzed by Feige and Kilian [SIAM J. Comput., 30 (2000), pp. 324--346] but with simpler analysis and exponentially better soundness error.

Madhu Sudan is the recipient of the 2002 Nevanlinna Prize. Sudan has made fundamental contributions to two major areas of research, the connections between them, and their applications. The first area is Coding Theory. Established by Shannon and Hamming over 50 years ago, it is the mathematical study of the possibility of and the limits on reliable communication over noisy media. The second area is Probabilistically Checkable Proofs (PCPs). By contrast, it is only 10 years old. It studies the minimal resources required for probabilistic verification of standard mathematical proofs. My plan is to briefly introduce these areas, their motivation and foundational questions, and then to explain Sudan’s main contributions to each. Before we get to the specific works of Madhu Sudan, let us start with a couple of comments that will set up the context of his work.

Soft errors caused by radiation particles are becoming an increasingly important issue for memory reliability. Traditionally, Single Error Correction (SEC) codes have been used to correct soft errors. Such codes can correct one error per memory word, but as errors become more frequent they may be insufficient. More complex error correction codes (ECCs) could be used, but they typically require complex decoders which impact memory area and speed. In this paper, the use of Euclidean geometry (EG) Codes for memory applications is studied. The results show that these codes, which provide powerful error correction capabilities, can be implemented efficiently in terms of area and latency.

We introduce and study the notion of probabilistically checkable proofs (PCP) for real number algorithms. Our starting point is the computational model of Blum, Shub, and Smale (BSS) and the real analogue NPR of NP in that model. We define in a straightforward manner verifiers as well as complexity classes PCPR(r(n),q(n)) for the BSS model. Our main result is, to the best of our knowledge, the first PCP theorem for NPR. It states that each problem in NPR has transparent long proofs, i.e.,NPR \subseteq PCPR(poly,1), where poly denotes the class of univariate polynomial functions. The techniques used extend ideas from [12] for self-testing and self-correcting certain functions over so-called rational domains to more general domains over the real numbers. The latter arise from the particular NPR-complete problem for which we construct a verifier of the required form.

A basic goal in property testing is to identify a minimal set of features that make a property testable. For the case when the property to be tested is membership in a binary linear error-correcting code, Alon et al. [N. Alon et al., 2003] had conjectured that the presence of a single low weight code in the dual, and "2-transitivity" of the code (i.e., the code is invariant under a 2-transitive group of permutations on the coordinates of the code) suffice to get local testability. We refute this conjecture by giving a family of error correcting codes where the coordinates of the codewords form a large field of characteristic two, and the code is invariant under affine transformations of the domain. This class of properties was introduced by Kaufman and Sudan [2008] as a setting where many results in algebraic property testing generalize. Our result shows a complementary virtue: this family also can be useful in producing counterexamples to natural conjectures.

Non-volatile memories are paid attention to as a promising alternative to memory design. Data stored in them still may be destructed due to crosstalk and radiation. We can restore the data by using error-correcting codes which require extra bits to correct bit errors. Further, non-volatile memories consume ten to hundred times more energy than normal memories in bit-writing. When we configure them using error-correcting codes, it is quite necessary to reduce writing bits. In this paper, we propose a method to generate a bit-write-reducing code with error-correcting ability. We first pick up an error-correcting code which can correct t-bit errors. We cluster its codeswords and generate a cluster graph satisfying the S-bit flip conditions. We assign a data to be written to each cluster. In other words, we generate one-to-many mapping from each data to the codewords in the cluster. We prove that, if the cluster graph is a complete graph, every data in a memory cell can be re-written into another data by flipping at most S bits keeping error-correcting ability to t bits. We further propose an efficient method to cluster error-correcting codewords. Experimental results demonstrate that, when we apply our bit-write-reducing code to MediaBench applications, it can reduce writing-bit counts by up to 28.2% and also energy consumption of non-volatile memory cells by up to 27.9% compared to existing error-correcting codes keeping the same error-correcting ability. This paper proposes the world-first theoretically near-optimal bit-write-reducing code with error-correcting ability based on the efficient coding theories.

As the size of on-chip SRAM caches is increasing rapidly and the physical dimension of the SRAM devices is decreasing, reliability of caches is becoming a growing concern. This is because with increased size of caches, the likelihood of radiation-induced soft faults also increases. As a result, information redundancy in the form of Error Correcting Codes (ECC) is becoming extremely important, especially to protect the larger sized last level caches (LLCs). In typical ECCs, extra redundancy bits are added to every row to detect and correct errors. There is additional encoding (while writing data) and decoding (while reading data) procedures required as well. In caches, these additional area, power and latency overheads need to be minimized as much as possible. To address this problem, we present in this paper Parity++: a novel unequal message protection scheme for last level caches that preferentially provides stronger error protection to certain "special messages". This protection scheme provides Single Error Detection (SED) for all messages and Single Error Correction (SEC) for a subset of messages. Thus, it is stronger than just a basic SED parity and has much lower parity storage overhead (4X lower for a 64-bit memory) and lower error detection energy than a traditional Single Error Correcting, Double Error Detecting (SECDED) code. We also evaluate Parity++ with a memory speculation procedure that can be used with any ECC scheme to hide the decoding latency while reading messages when there are no errors.

Since no communications network can guarantee error-free transmission, most communications systems include hardware or software to detect and correct transmission errors. Error correcting codes are now routinely used in communication systems to ensure data integrity in storage and transmission. As electronic communications become more widespread, the market for error correcting codes should greatly expand and the demand for improved coding techniques should increase. OSCI is developing decoders for a family of error-correcting codes known as Hermitian codes. The purpose of this CRADA project was to evaluate the performance of a parallel version of the OSCI decoder for an 8-bit Hermitian code and to describe a possible electronic implementation of the decoder based on the algorithm’s data dependency graph.

Emerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct few errors in a few nanoseconds. The low latency is necessary to meet the DRAM-like and/or eXecuted-in-Place requirements of Storage Class Memory devices. In this paper we design an ECC decoder of a shortened BCH code with 256-data-bit page able to correct three errors in less than 3 ns. The tight latency constraint is met by precomputing the coefficients of carefully chosen Error Locator Polynomials, by optimizing the operations in the Galois Fields and by resorting to a fully parallel combinatorial implementation of the decoder. The latency and the area occupancy are first estimated based on the number of elementary gates.Eventually,the implementation of the solution by Synopsys topographical synthesis methodology in 54nm logic gate length CMOS technology gives a latency lower than 3ns and a total area less than250 · 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .