Towards Uniform Modeling and Holistic Testing of Hardware and Software

Until now, simulation has been the primary approach for the functional verification of register transfer level (RTL) circuit descriptions written in a hardware description language (HDL). A finite state machine (FSM) coverage test can find all the bugs in a FSM design. However, this is impractical for large designs because of the state explosion problem. In this paper, we modify the higher-level FSM models used in other applications to replace the FSM model in the FSM coverage test. The state transition graphs (STGs) can be significantly reduced in this model, so that the complexity of the test becomes acceptable even for large designs. This model can be easily extracted from the original HDL code automatically, with little computation overhead. Experimental results show that it is indeed a promising functional test for FSMs.

The implementation of Finite State Machines (FSMs) is a recurring task in the development of embedded systems when Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) are being designed. The standard implementation language for these FSMs in this context is a Hardware Description Language (HDL) like VHDL or Verilog. The implementation complexity can rise quickly depending on FSM size and which devices/components are controlled. In many cases FSMs enforce sequential execution of instructions in the concurrent world of FPGAs or ASICs.This paper proposes the use of a MIPS-based assembly dialect and assembler called aFSM to decrease the implementation complexity of such FSMs by automatically generating the FSMs VHDL code. A human VHDL implementation of an Ethernet controller with an FPGA is compared against the implementation with aFSM to evaluate the assembler.

The study focuses on efficient design and integration of Silicon Intellectual Properties (SIPs), as well as measurement of SIP physical signals to meet the following three objectives: 1. efficient design of master and slave wrappers by using the Unified Modeling Language (UML) model to describe System on Chip (SoC) bus behavior; 2. an SoC integration framework including master and slave SIP templates, memory controller, DMA and SoC bus analyzer to accelerate SoC integration; and 3. an SoC bus analyzer measuring physical hardware signals for bus protocol specification testing and thus to alleviate debugging from physical to system levels in the process of SoC integration. We exploit the Real-Time UML (RT-UML), SoC bus governed FPGA platform, and a waveform viewer reading test benches described in standard Hardware Description Language (HDL) such as Verilog. The RT-UML achieves fast design of master/slave wrappers, the FPGA platform reaches fast SoC integration with physical hardware prototype, and the waveform viewer accomplishes real world signal analysis. We begin at SDRAM controller and successfully transplant it to the FPGA platform. Firstly according to SDRAM specifications, we modify timing parameters according to the AC electrical characteristics. Secondly, according to the waveform defined in the AMBA specification, we draw out the Message Sequence Chart (MSC), and in accordance with the MSC we generate parameterized Finite State Machines (FSMs) for wrappers. Regarding the parameterized wrapper FSMs as templates, we wrap the SDRAM controller into an AMBA-compatible slave SIP. The AMBA SoC bus Analyzer, without interposing the bus transactions among SIPs under test, captures bus signals to external SDRAM. With programmable triggering conditions in complex logic, SoC engineers dump the signals before and after triggered point and analyze protocol compatibility using the waveform viewer. In this way, DMAs and user-defined ASICs are easily wrapped into platform-based and truly reusable SIPs. With the wrapper templates and the analyzer, we develop two types of direct memory access (DMA) prototypes including an independent DMA master/slave SIP and a dedicated DMA control framework that is integratible into memory-intensive SIPs. The wrapper templates, DMA prototypes, and the SoC bus analyzer constitute a reconfigurable SoC design framework. The statistical analysis suggests that the SoC design flow includes the proposed framework and gradually integrates verified SIPs. Therefore, providing real-world hardware rapid prototyping, the proposed framework effectively reduces complexity and uncertainty while increases reliability of SoC integration before the backend design stage.

Synthesis of finite state machines for improved state verification

This paper presents the design of traffic controller hardware using fuzzy expert system algorithm for traffic light controlling purpose. The process uses the knowledge base of a Fuzzy System - rule base and parameters. This knowledge based system aspect makes the design more simple and efficient, especially when compared with traditional trial and error methods. A functional Fuzzy Traffic Controller (FTC), which utilises fuzzy logic algorithm to achieve a smart and a flexible knowledge-based system in hardware design while achieving better efficiency in the traffic control and minimizing traffic jam occurrences at interchange on road area. We describe a hardware platform for evolving system by using knowledge base of a Fuzzy System. To develop the system, the behaviour level of FTC algorithm has developed using Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) under MAX+PLUS II CAD environment. The Finite State Machine (FSM) of the FTC has been coded in VHDL program for controlling the specific traffic flow application. Later on, the FPGA Express (Synthesis tool) has used to get a fully gate level synthesis architecture for the whole Fuzzy based hardware chip. The designed codes of the FTC have downloaded onto the UP1 FPGA (Field Programmable Gate Array) Educational board (Altera FLEX10K) for verifying the FTC hardware chip functionality. The performance of an expert fuzzy system based chip for controlling traffic light is evaluated.

Software-hardware co-design enabled with co-simulation is useful for building embedded computing systems. Indispensable to design is developing hardware and software simulation models at appropriate abstraction levels. Toward this goal, this paper presents a study of combined Register-Transfer-Level (RTL) and software system modeling. Specifically, composition of hardware and software models is proposed and a co-simulation environment to simulate the models is developed. The hardware and software parts of a prototypical Network on Chip (NoC) system are modeled and simulated. The hardware part is specified at RTL level using the DEVS Suite Simulator and the software part defined as a MATLAB script. A Functional Mock-up Interface (FMI) is developed for the DEVS-Suite Simulator to support hardware and software model coupling and co-simulation. This study details a modular development of hardware and software models executing on disparate environments instead of employing a monolithic modeling method supported with a monolithic simulation engine.

This paper summarizes recent patents related to the use of graphical programming languages for the development of embedded computing applications. Patents in three specific areas of application are described in the paper. The first set of patents relates to general aspects of using graphical programming for applications targeted to embedded devices. The second area relates to the use of graphical programming environments to enable representations of system behavior using domain-specific “models of computation.” These models of computation may include control block diagrams, statecharts, textual math, etc. The third application area is the use of a graphical programming language to represent system behavior that may be targeted to any of a plurality of different embedded devices. In this case, the system behavior is abstracted to a general form and is not written in a manner that is specific to a particular device. Finally, the current and future developments in the field are briefly discussed. Keywords: Graphical programming, embedded programming, embedded computing, statechart, finite state machine, hardware description language (HDL), field-programmable gate array (FPGA), microprocessor, digital signal processor (DSP), real-time

Scan flip -- flop insertion for aiding design for testability invites additional hardware overhead, thereby deteriorating the performance of the circuit. In this paper, we shall demonstrate a novel FPGA based implementation of inserting scan registers in commonly used Finite State Machines and pipelined data path circuits with no hardware overhead or compromise in performance. All our proposed designs have been realized using a relatively low -- level design methodology involving target FPGA family based primitive instantiation, coupled with their constrained placement on the Xilinx FPGA fabric. Implementation results clearly reveal the superiority of our proposed architectures in comparison to equivalent circuits derived through behavioral modeling with respect to area and speed. Additionally, our proposed scan register inserted circuits compare favourably with circuits designed without the scan flip -- flops. Coupled with this, lies the ease of an automated generation of the corresponding Hardware Description Language (HDL) and placement constraints and their portability among other advanced FPGA families from Xilinx.

The large size and complexity of the modern digital hardware impose great challenges to design and validation. Hardware Description Languages (HDLs) and System-Level Description Languages (SLDLs) rely on sequential discrete event semantics. Parallel Discrete Event Simulation (PDES) has recently gained extensive attention for parallelizing these languages due to the ever-increasing complexity of embedded and cyber physical systems. However, PDES application has not yet reached acceptable maturity and pervasiveness for accelerating computer architecture problems. This is due to inherent complexity of hardware components that require using different advanced PDES techniques. In this paper, we look at the main problem from a radically different angle. First, we suppose there is only a single universal discrete event model of computation for simulation purely defined by distributed optimistic PDES, i.e., logical-process-based event scheduling worldview. Second, we construct a new parallel system-level simulation language called OSML for ESL. Third, we propose a unified Cloud-based CAD tool called Troodon to automatically parallelize existing hardware languages atop OSML. To the best of our knowledge, OSML is the first work on optimistic synchronization applied to hardware-specific SLDLs and hardware models at different levels of abstraction in ESL, which contain complex data structures by proposing a hybrid checkpointing scheme.

This chapter presents the synthesis of synchronous control logic to activate the functional units in the data-path according to a given schedule. Control synthesis is important because it affects the control flow of operations and hence directly impacts the overall performance of the resulting hardware. There are many different styles of control implementation, ranging from ROM-based microprogrammed controllers [SLP88] to finite-state machines [CR89] to distributed control [BCM+ 88]. In the simple case where the hardware model either does not contain any data-dependent delay operations or does not support multiple threads of concurrent execution flow, the control logic can be implemented using a microprogrammed controller or a single finite-state machine in a straightforward way.

Software testing is one of important phase in software development. The capabilities of t-way testing to cater bugs due to interactions while reducing the test suite size compare to exhaustive testing has been proven in past decades. However, the execution’s time of the t-way strategy also should be given attention as it could increase the productivity of the testing phase. Thus, this paper proposed a tune version of ant colony optimization algorithm (TACO). TACO is metaheuristic strategy where it adopts ant colony optimization in generating test suites. As further improvement, TACO also integrated with fuzzy logic to dynamically select amount of ant in the algorithm. TACO able to supports uniform strength t-way testing. Experiment result shows that TACO produce a remarkable result of test suite size and execution’s time compared to other strategy for uniform strength t-way testing.

Researchers have proposed different methods for testing digital systems and circuits in the last couple of decades. The need for testing digital logic circuits has become more important than ever due to the growing complexity of such systems. During the design phase, testing is focusing on design defects, as well as manufacturing and wear out type of defects. Failures in digital systems could be caused, for example, by design errors, the use of inherently probabilistic devices, and manufacturing variability. As a way to test digital systems in a more efficient way, automated test generation has been proposed to automatically create tests that can quickly and accurately identify faulty components. Examples of such techniques are the sequential test generation, the scan path testing, and the random test generation techniques. With the research domain becoming more mature and growing, it is essential to systematically identify, analyze, and classify these contributions. We performed a systematic mapping study of automated test generation for digital circuits aimed at providing an overview of the application of these techniques. We focused on three of the most widely-used and well-supported hardware description languages (HDLs) for digital systems: Verilog, SystemVerilog, and VHDL. Our results suggest that the majority of the test generation methods for digital circuits are focused on the behavioral and register-transfer design levels. Fault-independent and fault-oriented test generation are the most frequently reported types of test generation methods, while HDL model simulation is the most common test generation technology used to search for test cases in these academic studies. While the results are suggesting a growing interest in this area, the majority of articles are published as conferences papers. Our results show that only 31% of the methods are implemented as software tools and only 63% of all contributions are actually generating executable test cases. This study makes three important contributions, (i) a state-of-the-art of test generation for digital system designs research is provided, (ii) the reported characteristics are identified in both the primary papers and experimental reports, (iii) gaps and opportunities for future test generation for digital system designs research are identified.

In the RF and mixed signal IC design, Built in Self Test (BIST) technique is becoming an important issue that affects both the time-to-market and product cost of many modem electronic systems. In most cases, these systems are evaluated and designed with electrical stimulation method. The main problem of electrical simulation tools is that the extraction of the parameters associated with the performances of circuit and the design rules depend broadly on the intuition of the experts. To overcome this problem, an efficient methodology for top-down design, modeling, and simulation of complete BIST circuit to validate its proper function before moving on to transistor level implementation is presented in this paper. The described method is based in behavioral modeling strategy using hardware description language VHDL-AMS. At behavioral level, the performances of circuits are optimized by modeling and simulation these performances parameters with a hardware description language without considering its transistor level implementation. Hence, methods and algorithms for modeling has been developed, for simulation, in order to decrease the total simulation time, validation of systems, and accelerate the production cycle of electronic devices. The proposed BIST schema based on modeling and simulation strategy is applied to test a loop filter. Extensive simulation study shows that the proposed BIST approach can efficiently detect the loop filter fault and tolerate this type of fault, and so offers high fault coverage of 100% for the fault detects.

The Instruction Set Processor Specifications (ISPS) computer description language is an evolutionary step towards the formalization of the digital design process at the higher or behavioral levels. It has been used as a design tool, which covers a wider area of application than any other hardware description language. Thus, besides simulation and synthesis of hardware, software generation program verification, and architecture evaluation and control are among the current applications based on ISPS. The range of current and contemplated application areas are proof of the usefulness of the notation and its extension mechanisms. ISPS supports a wide range of applications, rather than a wide range of design levels. Thus, this paper is divided into two parts. The first part describes the notation, its intended use, and the extension mechanisms which allow multiple applications or areas of research to co-exit and share machine descriptions. The second part describes some of the current applications for ISPS.

A high-level language for design and modeling of hardware