Versatile COFDM demodulator design based on the CORDIC-algorithm

Frequency synthesizer has been used in numerous communication applications. This is acknowledged as the heart of the electronics systems. Numerically controlled oscillator (NCO) is the primary part of this frequency synthesizer, which helps in generating high precision & high frequency signal. One of the best suited methods to empower the NCO is CORDIC algorithm. CORDIC (Coordinate Rotation Digital Computer) algorithm is one of the well-known methods used for the trigonometric & arithmetic calculation and applications of digital signal processing. This algorithm can work with higher efficiency for the signal generation & hardware utilization. CORDIC architecture is used in the NCO, which is the central part of DDFS (Direct Digital Frequency Synthesis) to produce analog signal. Here in this paper, a sinusoidal waveform generator is implemented using an efficient 16-stage pipelined CORDIC architecture with a very small look-up table (LUT). The architecture is designed, and its RTL simulation is carried out using Xilinx Vivado. The purpose of the work is to improve the output frequency and the accuracy. The architecture had been implemented on a Xilinx Spatran-6 (XC6SLX9) FPGA & the final results showed that the proposed pipelined architecture is capable of generating a maximum output frequency of 157.684 MHz with less than 1% (approximately 0.34%) of error.

Digital Down Conversion (DDC) is a fundamental process in software defined radio (SDR) and digital communications, which transforms intermediate frequency (IF) signals into baseband signals. In conventional DDC designs, multipliers and look-up tables are generally employed, both of which tend to increase hardware size and power consumption. In this paper we present a Dual-Mode CORDIC-Based DDC architecture which uses the CORDIC (Coordinate Rotation Digital Computer) algorithm to eliminate multipliers. This novel architecture combines a CORDIC-based Numerically Controlled Oscillator (NCO), a CORDIC mixer, and a Cascaded Integrator-Comb (CIC) filter with a finite impulse response (FIR) com pentation filter. The NCO provides two precision modes - an 8-stage low-latency mode for speed and a 16-stage high precision mode for accuracy, giving runtime reconfigurability according to design requirements. Simulations and analysis show that the design gives highly accurate frequency translation, is efficient in hardware utilization and fully eliminates the use of digital signal processing (DSP) blocks. Overall, the architecture proposed offers a low-power, low-cost, and recon figural solution ideal for modern SDR-based applications and flexible digital signal processing systems.

The growth of high-density television (HDTV) systems, along with the development of peripheral devices, depends on the development of transmission systems. The authors have constructed an HDTV digital transmission system for the purpose of supporting secondary distribution of HDTV signals and developed an HDTV codec intended for application in this system. The HDTV digital transmission system is a transmission system that utilizes a single (36 MHz) channel of a Kuband transponder of a communication satellite, employs a rate 3/4 convolutional code and a (255,239) Reed-Solomon block code for forward error correction, and uses quadriphase-shift keying (QPSK) as the modulation format. The HDTV codec developed for application in this system is a coding method that is based on discrete cosine transform (DCT) and motion compensated prediction, which provides 40 Mb/s coded video signal. In this paper, the structure of the HDTV digital satellite transmission system and the HDTV codec are described. The video coding method of the HDTV codec is also described. © 1997 Scripta Technica, Inc. Electron Comm Jpn Pt 1, 80 (1): 35–51, 1997

The Coordinate Rotation Digital Computer (CORDIC) algorithm has emerged as a pivotal method for executing trigonometric and various mathematical operations within digital systems. Field-Programmable Gate Arrays (FPGAs) have witnessed a remarkable surge in adoption for implementing the CORDIC algorithm owing to their inherent flexibility and exceptional performance capabilities. This paper endeavours to provide a comprehensive overview of FPGA implementations of the CORDIC algorithm, elucidating both the advantages and challenges associated with this methodology. It thoroughly examines various FPGA architectures customized for CORDIC implementation, meticulously analyzing their respective trade-offs regarding resource utilization, performance metrics, and accuracy levels. Moreover, the paper explores numerous applications where the FPGA-based CORDIC algorithm shines, illustrating its adaptability across diverse domains like digital signal processing and control systems. These applications underscore the algorithm's efficacy in addressing real-world challenges and its potential to significantly augment system performance and efficiency.By furnishing profound insights into FPGA-based CORDIC implementations, this paper serves as an invaluable resource for engineers and researchers keen on harnessing the capabilities of FPGAs for high-performance mathematical computations in digital systems.

This paper presents the implementation of KA algorithm and Coordinate Rotation Digital Computer (CORDIC) structures for adaptive digital signal processing. Adaptive FIR filter is used in RADAR to detect weak RADAR signal. Implementation of FIR Adaptive filter requires more hardware and power consumption. Several optimization techniques are proposed to reduce hardware, power consumption and increase the speed. The optimization algorithm used in FIR Adaptive filter are Vedic mathematics, CORDIC algorithms, KA algorithm e.t.c. Among these algorithm CORDIC algorithm are widely used in RADAR application due to it's simple architecture and processor independent nature. CORDIC structures are implemented using shifter and adder. Compared to MAC unit CORDIC structures have less chip area and high speed. Further the speed and chip area of CORDIC structure is improved by combining CORDIC with KA architecture. The larger computation is splitted into smaller computation unit using KA algorithm and the computation operation is performed without multiplier using CORDIC structures, hence overall speed and chip area are improved.

The coordinate rotation digital computer (CORDIC) is a class of shift-add algorithm for the rotation of vectors on a plane. The major problem in this CORDIC algorithm is the linear rate of convergence with the speed of the iteration. The main aim of the improved CORDIC algorithm is to utilise an integrated adder subtractor in place of binary adder subtractor to decrease the count of iterations and hardware reduction technique. The improved CORDIC splits the rotation angle into several series of micro-rotation angles to calculate the rotation and the new set of angle provides a fast convergence. The canonical signed-digit (CSD) approach together with Hcub algorithm employs for the number of adder subtractor reduction and shifters in CORDIC architecture design. The performances of the proposed CORDIC design have been verified by employing it in FFT implementation. The simulation result indicates the higher frequency of 77.20%, 82.78%, 78.30% and 76.57% when compared with conventional methods. The evaluation of FFT is also done by comparing with the conventional methods. The power consumption, number of iterations and the hardware complexity reduced by using the improved CORDIC and the working of this proposed algorithm is evaluated through the FPGA implementation.

An arithmetic processor is designed based on redundant constant-factor implementation of the coordinate rotation digital computer (CORDIC) algorithm with three different modes: circular, hyperbolic and linear. Both CORDIC types (angle calculation and vector rotation) are considered in this unified processor that is capable of computing a wide variety of arithmetic and elementary functions including: multiplication, division, some common trigonometric functions, natural logarithms, square roots, vector norm and phase. Furthermore, by merging the scaling operation with the regular CORDIC iterations, the processor based on folded (iterative) CORDIC architecture reduces by about 1/4 the total number of iterations in one complete CORDIC operation.

Modulation and Demodulation are the most critical blocks in a communication system. Demodulators used in coherent communication receivers not only get back the message signal, but also perform phase error detection and correction. Phase error detection and correction involves tuning or adjusting the phase of the reference signal to that of the carrier signal received. This is an iterative process. One of the popular techniques employed for phase error detection and correction is the Costas Loop. There has been research about Numerically Controlled Oscillators (NCO) based on CORDIC algorithm being used in a Costas Loop [1]. The other simple yet memory expensive alternative to the CORDIC algorithm is to use a LookUp Table (LUT) based technique. This paper tries to model a Costas Loop based on each of the methods separately and then compare the results. There has been notable work involving the use of symmetric FIR filters in a Costas Loop [2] which saves on memory. However there has been no attempt to compare the results of folded filter (uses one half of the filter coefficients only) architecture versus that obtained from unfolded filter (uses the entire coefficient sequence) architecture implementations. This paper compares the results obtained from folded filter implementation versus that obtained from unfolded filter implementation. The system was simulated using MATLAB and Simulink. The Verilog implementation was programmed on Spartan 3e FPGA board.

ICITAL transmission systems of all types are of great current interest as we embark on the information age. For any new transmission system, the topology, components, and system parameters are determined by many and various techniques. They are chosen not only by explicit, deductive technical reasoning, but also by the art of engineering, the desire for continued product line compatibility, patents possessed or not possessed, and new technology. Nonetheless, most digital transmission systems are made up using one or more of the following components: a bandpass filter, low-pass filter, Nyquist filter, slope equalizer, cable equalizer, and transversal equalizer. These items are the subject of this article. It is ironic that digital transmission systems have a preponderance of such components-all necessary for analog signal conditioning of the digitally transmitted signal. In the myriad of digital transmission systems, two distinct approaches to filtering and equalization predominate: one for baseband systems and the other for frequency translated, or modulated, signal systems. This division results from the need to have a competitive system transmission efficiency to cost ratio: where transmission efficiency is transmitted bit rate/channel bandwidth (BR/BW). For baseband systems, as might be expected, the difficulties, and thus cost, of filtering and equalization increase with increased transmission efficiency. To obtain a favorable BR/BW to cost ratio, the bandwidth, an available quantity, is usually sacrificed to keep system costs low. Signal modulation is required when it is desired to simultaneously transmit several baseband signals over common transmission facilities using a frequency division multiplex scheme. A modulated signal system is also necessary when the transmission vehicle has a significant low-frequency limitation; as does, for example, the general customer premises-to-customer premises telephone connection. In such systems, costs start off high because of the additional modulation circuitry. Money can then be further spent on filtering and equalization to allow for increased transmitted bit rate in order to provide a more reasonable BR/BW to cost ratio. Based upon the above premise, the text expands further on the differences between filters and equalizers used for baseband and modulated digital transmission systems.

Views Icon Views Article contents Figures & tables Video Audio Supplementary Data Peer Review Share Icon Share Twitter Facebook Reddit LinkedIn Tools Icon Tools Reprints and Permissions Cite Icon Cite Search Site Citation William E. Glenn, Henry Helmken; Satellite distribution of digital compressed video audio and data. AIP Conf. Proc. 25 January 1995; 325 (1): 83–89. https://doi.org/10.1063/1.47256 Download citation file: Ris (Zotero) Reference Manager EasyBib Bookends Mendeley Papers EndNote RefWorks BibTex toolbar search Search Dropdown Menu toolbar search search input Search input auto suggest filter your search All ContentAIP Publishing PortfolioAIP Conference Proceedings Search Advanced Search |Citation Search

Digital communication plays a vital role in today’s communication system in this electronic world. However, the applications of digital communication are limited due to the requirements of antenna with fully programmable circuits having modulators and de-modulators. It may also end with hardware complexities. In order to overcome such complexities, a universal modulator is designed with an efficient iterative method named as CORDIC algorithm in prior methods. Although, the CORDIC (Coordinate Rotation Digital Computer) algorithm works efficiently, it leads to computational as well as memory complexities. Additionally it creates a need for latency reduction strategy. Therefore, to compete with all these issues faced with the prior method, we proposed an amended CORDIC algorithm in universal modulator working with the principle of the harmonized Stone–Weierstrass theorem. In addition, the Newton–Raphson method and Remz algorithm are introduced here to reduce the memory complexity by doubling the number of iterations and to select the best carrier signal, respectively. Thus, our proposed work effectively unravels all the notorious issues caused with the conventional CORDIC algorithm and the proposed universal modulator is implemented in Xilinx.

Objective: The objective of this work is to efficiently implement a Co-ordinate Rotation Digital Computer (CORDIC) based fast algorithm for power of two length DCT. Methods: The proposed algorithm has some advantages such as regular Cooley-Tukey FFT like data flow, post scaling factor and arithmetic-sequence rotation angles. Using CORDIC algorithm, different types of DCT like four point, eight point and inverse eight point are derived. Usage of trigonometric formula reduces the number of CORDIC. By reusing uniform processing Element cells, architecture for 8-point CORDIC DCT is developed. This is an efficient method for overcoming the problem of lack of synchronization among various rotation angles. Findings: When compared with other known architectures, the proposed 8-point DCT architecture is more efficient in terms of power and area. Power analysis and area estimation are performed for the designed architectures and then further power reduction is carried out using clock gating technique. A power reduction of 4.29% is achieved. The area is also reduced by 0.29%. Conclusion: An efficient VLSI implementation for 8-point DCT by reusing the uniform processing element cells with low hardware complexity is developed.

In the literature, multiplexer has been proposed for the ASIC implementation of unrolled CORDIC (COordinate Rotation DIgital Computer) processor. In this paper, the efficacy of this approach is studied for the implementation on FPGA. For this study, both non pipelined and 2 level pipelined CORDIC with 8 stages and using two schemes - one using adders in all the stages and another using multiplexers in the second and third stages. A 16 bit CORDIC for generating the sine/cosine functions is implemented using all the four schemes on both Xilinx Virtex 6 FPGA(XC6VLX240) and Altera Cyclone II FPGA(EP2C20F484C7). From the implementation results, it is found that the nonpipelined and pipelined CORDICs using multiplexer requires 1.6, 1.4 times lower area in Xilinx FPGA and 1.8, 1.6 times lower area in Altera FPGA than that using only adders. This is achieved without reduction in speed.

This paper presents an efficient approach for computing the N-point (N=2/sup n/) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture.

The hardware implementation of a magnitude estimation algorithm for a hearing aid is presented in this paper. Digital signal processing (DSP) is used in almost all the modern digital hearing aids available today. The processing of the sound signals is carried out in the frequency domain. Fast Fourier transform (FFT) converts the time domain signal to frequency domain and gives a complex number output representing each frequency component in the audible frequency spectrum. The magnitude estimation block estimates the magnitude of these complex numbers. This estimated magnitude is used as an input to apply various DSP algorithms for sound processing in the hearing aid. In this paper the Alpha max-Beta min and the coordinate rotation digital computer (CORDIC) algorithms for magnitude estimation of a complex number are compared from the hardware implementation point of view. The emphasis of this paper is the hardware implementation of the CORDIC algorithm in application specific integrated circuit (ASIC) design flow and its performance analysis. The CORDIC algorithm is implemented because of its accuracy and implementation simplicity. The paper also presents the simulation and synthesis results obtained for hardware implementation of four iterations of the CORDIC algorithm for magnitude estimation.