A low-area based costas loop implementation for BPSK signals

Frequency synthesizer has been used in numerous communication applications. This is acknowledged as the heart of the electronics systems. Numerically controlled oscillator (NCO) is the primary part of this frequency synthesizer, which helps in generating high precision & high frequency signal. One of the best suited methods to empower the NCO is CORDIC algorithm. CORDIC (Coordinate Rotation Digital Computer) algorithm is one of the well-known methods used for the trigonometric & arithmetic calculation and applications of digital signal processing. This algorithm can work with higher efficiency for the signal generation & hardware utilization. CORDIC architecture is used in the NCO, which is the central part of DDFS (Direct Digital Frequency Synthesis) to produce analog signal. Here in this paper, a sinusoidal waveform generator is implemented using an efficient 16-stage pipelined CORDIC architecture with a very small look-up table (LUT). The architecture is designed, and its RTL simulation is carried out using Xilinx Vivado. The purpose of the work is to improve the output frequency and the accuracy. The architecture had been implemented on a Xilinx Spatran-6 (XC6SLX9) FPGA & the final results showed that the proposed pipelined architecture is capable of generating a maximum output frequency of 157.684 MHz with less than 1% (approximately 0.34%) of error.

Digital Down Conversion (DDC) is a fundamental process in software defined radio (SDR) and digital communications, which transforms intermediate frequency (IF) signals into baseband signals. In conventional DDC designs, multipliers and look-up tables are generally employed, both of which tend to increase hardware size and power consumption. In this paper we present a Dual-Mode CORDIC-Based DDC architecture which uses the CORDIC (Coordinate Rotation Digital Computer) algorithm to eliminate multipliers. This novel architecture combines a CORDIC-based Numerically Controlled Oscillator (NCO), a CORDIC mixer, and a Cascaded Integrator-Comb (CIC) filter with a finite impulse response (FIR) com pentation filter. The NCO provides two precision modes - an 8-stage low-latency mode for speed and a 16-stage high precision mode for accuracy, giving runtime reconfigurability according to design requirements. Simulations and analysis show that the design gives highly accurate frequency translation, is efficient in hardware utilization and fully eliminates the use of digital signal processing (DSP) blocks. Overall, the architecture proposed offers a low-power, low-cost, and recon figural solution ideal for modern SDR-based applications and flexible digital signal processing systems.

Investigation of Costas loop phase deviation effect on BER performance of space downlink coherent communication system with DPSK scheme

Numerically Controlled Oscillator (NCO) is an important components in many Digital Communication Systems such as Digital Radio and Modems, Software Defined Radios, Digital Down/Up converters for Cellular and PCS base stations etc. A common method for digitally Generating a complex or Real valued sinusoid employs a Look-Up table based scheme. The NCO Design is first simulated and optimized on the software tool Xilinx 10.1 and then coded in VHDL for Hardware Realization. The Designs are tested on Xilinx Spartan2 FPGA Development Platform. The test Results are matching with theoretical and simulated results. This paper presents a FPGA-based Implementation method which can greatly improve the performance, shorten development cycle and reduces cost. Keywords - Numerically Controlled Oscillator, FPGA, Look-up table, Register

The wide application of digital radio communication systems in recent years has resulted in increasing demands for allocated frequencies and, due to the overcrowded spectrum, interference has become a crucial problem. In many cases, such interference appears in the upper sideband or in the lower sideband of the useful signal. In the present paper a binary PSK communication system with interference in either the upper or the lower sideband is considered and a method of interference cancellation is proposed for the Costas loop widely used in PSK receivers. Experiments are conducted to demonstrate the efficiency of this method. The results show that the maximum cancellation with a simple circuit added to the Costas loop is 23 dB if Af (the difference between the frequencies of the PSK carrier and the interfering signal) is above 0.3 fβ (fβ the data bit rate). At the same time, the bit error rate in the digital signal is greatly improved. Also, with respect to the impairment due to jitter caused by interference, the performance of the Costas loop is practically unchanged within the specification range of an ordinary Costas loop. The advantages of the present method are that the circuit is simple, it is stable because there is no feedback in the interference cancellation part and the cancellation is effective even for interfering signals of unknown δf.

This paper presents the implementation of KA algorithm and Coordinate Rotation Digital Computer (CORDIC) structures for adaptive digital signal processing. Adaptive FIR filter is used in RADAR to detect weak RADAR signal. Implementation of FIR Adaptive filter requires more hardware and power consumption. Several optimization techniques are proposed to reduce hardware, power consumption and increase the speed. The optimization algorithm used in FIR Adaptive filter are Vedic mathematics, CORDIC algorithms, KA algorithm e.t.c. Among these algorithm CORDIC algorithm are widely used in RADAR application due to it's simple architecture and processor independent nature. CORDIC structures are implemented using shifter and adder. Compared to MAC unit CORDIC structures have less chip area and high speed. Further the speed and chip area of CORDIC structure is improved by combining CORDIC with KA architecture. The larger computation is splitted into smaller computation unit using KA algorithm and the computation operation is performed without multiplier using CORDIC structures, hence overall speed and chip area are improved.

Image formation algorithms in a variety of applications have explicit or implicit dependence on a mathematical model of the observation process. Inaccuracies in the observation model may cause various degradations and artifacts in the reconstructed images. The application of interest in this paper is synthetic aperture radar (SAR) imaging, which particularly suffers from motion-induced model errors. These types of errors result in phase errors in SAR data, which cause defocusing of the reconstructed images. Particularly focusing on imaging of fields that admit a sparse representation, we propose a sparsity-driven method for joint SAR imaging and phase error correction. Phase error correction is performed during the image formation process. The problem is set up as an optimization problem in a nonquadratic regularization-based framework. The method involves an iterative algorithm, where each iteration of which consists of consecutive steps of image formation and model error correction. Experimental results show the effectiveness of the approach for various types of phase errors, as well as the improvements that it provides over existing techniques for model error compensation in SAR.

Following a description of the fast-Fourier-transformation (FFT) this paper discusses the advantages of the CORDIC-algorithm (coordinate rotation digital computer) compared to complex multiplication in butterfly-operations and NCOs (numerical controlled oscillator), which are often used in digital transmission systems. The implementation issues of the CORDIC-algorithm in programmable logic devices is illustrated by the example of a versatile transmission system for digital terrestrial television.

Digital communication plays a vital role in today’s communication system in this electronic world. However, the applications of digital communication are limited due to the requirements of antenna with fully programmable circuits having modulators and de-modulators. It may also end with hardware complexities. In order to overcome such complexities, a universal modulator is designed with an efficient iterative method named as CORDIC algorithm in prior methods. Although, the CORDIC (Coordinate Rotation Digital Computer) algorithm works efficiently, it leads to computational as well as memory complexities. Additionally it creates a need for latency reduction strategy. Therefore, to compete with all these issues faced with the prior method, we proposed an amended CORDIC algorithm in universal modulator working with the principle of the harmonized Stone–Weierstrass theorem. In addition, the Newton–Raphson method and Remz algorithm are introduced here to reduce the memory complexity by doubling the number of iterations and to select the best carrier signal, respectively. Thus, our proposed work effectively unravels all the notorious issues caused with the conventional CORDIC algorithm and the proposed universal modulator is implemented in Xilinx.

Since decades, CORDIC (Coordinate Rotational Digital Computer) has been drawing attention as an arithmetic unit in the field of signal and image processing, communication system and robotics due to its low hardware complexity to compute linear, trigonometric and transcendental functions. Because of increased demand of high dynamic range in the aforesaid application, the floating point CORDIC is an obvious choice instead of fixed point arithmetic. To the knowledge of authors, only up to double precision CORDIC's are reported in literatures which are limited to a dynamic range of 2-1023 to 21024 and have accuracy up to 13 decimal digits, but these existing CORDIC are also not enough to support the high dynamic range of values to be computed for aforesaid functions. Hence, authors in this paper have proposed a new quadruple floating point CORDIC architecture which have dynamic range of 2-16383 to 216384 and are accurate up to 22 decimal digit. This architecture could meet the demand of present and future dynamic range. This proposed design is coded and simulated using Verilog HDL and synthesized using XST tool, targeting a commercially available FPGA device XCVLX110T-IFF1136. Further, the hardware utilization with its timing and power performance are reported in this paper.

We propose a method to simulate impairments caused by the nonideal analog parts of the transmitter-receiver. They include for example a high-power amplifier (HPA), mixers, and oscillators. The major advantage in our approach is that the model parameters are adjustable and the system works in real time in the digital domain. Conventional methods have either not been real time, or they have been implemented with analog circuits. The HPA model is implemented with the coordinate rotation digital computer (CORDIC) algorithm for rectangular to polar translations. A look-up table (LUT) is used for AM/AM and AM/PM distortion. To minimize the size of the LUT we have used cubic spline interpolation. For phase noise of the oscillators we propose a simple rotation mode CORDIC implementation that does not need any complex multiplication. Only one field-programmable gate array (FPGA) circuit is needed to implement the power amplifier and phase noise models.

An efficient FPGA or ASIC based hardware implementation of deep neural networks face the challenge of limited chip area, and therefore an area efficient architecture is required to fully harness the capacity of parallel processing of FPGA and ASIC in contrast to general purpose processors. In literature, the challenges are to investigate a generalized mathematical model and architecture for neuron block in an ANN implementation. We have proposed a generalized architecture for neuron implementation based on the shift-and-add algorithm, collectively known as Coordinate Rotation Digital Computer (CORDIC) algorithm, having a wide range of application. The look-up-table (LUT) based approach with a shift-and-add algorithm is an alternative technique for polynomial approximation and implementation. Paper explains how the CORDIC algorithm works and investigates the power and area efficient versatile computational unit for ANN application. The derived model proves that for the hyperbolic tangent function required a double pseudo-rotation and additional subtraction compares to the sigmoid function. In this reference versatile approach based optimized sigmoid activation function is implemented. The function is synthesized and validate on Xilinx zynq XC7Z010clg400 SoC and result reveals the minimum resources utilization.

This paper presents a new recursive trigonometric (RT) technique for Field-Programmable Gate Array (FPGA) design implementation. The traditional implementation of trigonometric functions on FPGAs requires a significant amount of data storage space to store numerous reference values in the lookup tables. Although the coordinate rotation digital computer (CORDIC) can reduce the required FPGA storage space, their implementation process can be very complex and time-consuming. The proposed RT technique aims to provide a new approach for generating trigonometric functions to improve communication accuracy and reduce response time in the FPGA. This new RT technique is based on the trigonometric transformation; the output is calculated directly from the input values, so its accuracy depends only on the accuracy of the inputs. The RT technique can prevent complex iterative calculations and reduce the computational errors caused by the scale factor K in the CORDIC. Its effectiveness in generating highly accurate cosine waveform is verified by simulation tests undertaken on an FPGA.

In this work, Receiver Modules were developed and validated for 3G UMTS mobile communications downlink in Matlab. The modules were developed according to 3GPP Standards for downlink broadcast channel and are validated at each stage. Following modules were developed and validated-Synchronization code generator, Slot synchronization, Frame synchronization, Matched Filtering, Scrambling code generation, Descrambling, Spreading codes generation, Despreading, QPSK Demodulation, Phase and Frequency Error Estimation and Correction, Deinterleaving, Viterbi decoding and Cyclic redundancy check. This work can aid in further research and for the development of open source base station platforms for 3G UMTS mobile communications. The modules were validated with Keysight Base Station simulator and with 3G UMTS signal captured over the air.

Maintaining stable phasing in a linear accelerator is crucial for maintaining optimal performance. If phasing is incorrect, the beam will in general have an energy error and increased energy spread. While an energy error can be readily detected and corrected using position readings from beam position monitors at dispersion locations, this method is not useful for correcting energy spread in a system with many possible phase errors. While energy spread can be corrected by looking at beam size at a dispersive location, this typically involves a beam-intercepting diagnostic and is not compatible with top-up operation. Uncorrected energy spread results in poor capture efficiency in downstream accelerators, such as the Advanced Photon Source (APS) particle accumulator ring or booster synchrotron. To address this issue, APS has implemented beam-to-rf phase detectors in the linac, along with software for automatic correction of phase errors. We discuss the design, implementation, and performance of these detectors, as well as their use in feedback to automatically correct linac phase errors during top-up operation.