Virtual radios

This paper presents the use of the viciLogic viciLab tool suite for prototyping of audio digital signal processing (DSP) hardware on remote or locally connected PYNQ Systems on Chip (SoCs), along with flexible computer control software interfaces. The tool suite enables rapid prototyping of DSP hardware components, including demonstration, control and visualisation of components on local or remote hardware. Hardware components can be developed directly in existing hardware description languages (HDLs) or using higher-level design interfaces such as MathWorks HDL coder. Two configurable software control interfaces are presented: a low-level console builder facilitating fast graphical user interface (GUI) creation for hardware interaction, along with script-based automation; and a high-level Python-based GUI console creator integrates audio sampling, automated DSP hardware effect selection and SoC control, audio streaming and playback, and real-time waveform graphing. The two interfaces presented in this paper are illustrated through a series of DSP examples of increasing complexity: 8- and 16-tap FIR filters (with user-created VHDL model source); distortion and tremolo DSP functions (developed MathWorks HDL coder VHDL model source); and combinations of these components.

High power consumption and hardware cost are the two challenges for practical massive MIMO systems. One promising solution is to employ low resolution analog to digital converter (ADC). In this paper, massive MIMO relaying systems are investigated with double resolution ADCs at base station receiver, where some antennas are connected to low resolution ADCs, while the rest of the antennas are connected to high resolution ADCs. Closed form expression for uplink spectral efficiency (SE) is derived using the maximum ratio combining receiver assuming perfect channel state information. Some asymptotic analysis is discussed to explore the effects of system parameters on SE such as; the number of receive antennas, ADC quantization bits, user transmit power and the rate of high precision ADC in double resolution ADC structure. Moreover, energy efficiency with some system parameters is studied. It is shown that the performance wastage owing to low precision ADCs can be recompensed by growing the number of receive antennas $$ \varvec{N} $$, following a logarithmic scaling law instead of increasing the transmit power at both of source and relay. The double resolution ADCs can achieve a better tradeoff between power consumption and SE when using 4 quantization bits. By using only around 30 antennas, the double resolution ADCs achieves its optimal energy efficiency for selecting system parameters.

10 - Hardware and software development tools

Synthetic instruments apply the flexibility and computational capabilities of a digital signal-processing platform to synthesize a wide variety of synthetic instruments. The emphasis presented in traditional descriptions of a synthetic instrument is the architecture and the capabilities of the digital signal processing (DSP) platform and the user interfaces to the same. In this paper we highlight and discuss considerations of the signal conditioning and signal collection tasks. The focal point of the signal collection process is the analog-to-digital converter (ADC), the element that defines the precision and the bandwidth of the sampled data representation of the signal processed by the DSP platform. Analog signal conditioning prior to the ADC performs the task of limiting the input signal bandwidth and possible translation of the spectral band center. Digital signal conditioning following the ADC continues to perform the same tasks by further limiting the bandwidth of the digitized input signal as well as performing spectral translation with appropriate sample rate changes. In addition, the post conversion process can correct gain, phase, and time delay imbalances between input signal paths as well as gain and phase distortion encountered in the analog signal path. We identify and address performance constraints of existing ADCs and present a number of signal processing-based options to enhance and extend the operating regimes of the analog signal conditioning and the ADC conversion process.

A low power fuzzy logic based variable resolution ADC for wireless ECG monitoring systems

Today, DAW (Digital Audio Workstation) software lies at the heart of music production and has become an indispensable part of the industry. With the advancement of technology, music production is no longer confined to large studios but has also become accessible to individual users. Now, recording, mixing, and mastering processes can be carried out in a home environment using computer-based systems, without the need for expensive equipment. This fully digital workflow is referred to as "in-the-box" production. Technological developments have enabled individuals to produce music at a professional level in home studios, leading to the emergence of digital alternatives to analog devices. Digital processors have begun to replace analog equipment due to their cost-effectiveness and practicality. This study examines the differences between digital signal processors and analog devices in terms of usage, application areas, and sound processing methods. The research aims to compare digital and analog signal processors, particularly focusing on their processing methods, speed, flexibility, quality, and impact on sound. Based on the findings, it is concluded that digital signal processors, which are increasingly replacing analog processors in the music industry, do not possess the same characteristics as their analog counterparts.

The ultimate objective of Software Defined Radio (SDR) is to replace the entire analog signal processing in the wireless transceivers with digital signal processing. This will provide the flexibility, through reconfiguration or reprogramming, to enable the transceivers to work with different air-interfaces standards using a single generic hardware platform. Most of the research in SDR to date has been focused on base stations, which do not have as tight constraints in size and power consumption as handsets. However, in order to realize the promise of integrated services and global roaming capabilities, the design and development of a multi-standard SDR handset with dynamic reconfigurability is crucial. The size and power constraints imposed by handsets with limited resources pose a major design challenge. This special issue brings together 11 papers that address various aspects of this challenge from the perspectives of wireless systems, computing architectures, embedded systems and signal processing. The most important part of an SDR transceiver is the wideband analog-to-digital converter (ADC) that converts the radio frequency signal received by the antenna into digital form for further processing. The first paper, “A multi-mode sigma-delta ADC for GSM/WCDMA/WLAN applications” by Jose et. al. proposed a cascaded reconfigurable sigma-delta modulator that is able to work with three different communication standards. This design, implemented in 0.18 μm CMOS technology, exhibits excellent signal-to-noise plus distortion ratios and has reduced power consumption compared to conventional designs. After ADC, the digitized received signal will need to be separated into signals within the various bands specified by the communication standard. This is performed by the channelizer which has the highest computational requirements of the whole SDR system. The second paper, by Panicker et al., reviews the state-of-the-art filter bank channelizer techniques with low power and dynamic reconfigurability properties. The design of reconfigurable devices can be optimized using the methodology of parametrization which bring together the common aspects of a myriad number of wireless standards into a single processing procedure. In this way, the implementation of the multi-standard SDR will be greatly simplified. “Promising technique of parametrisation for reconfigurable radio, the Common Operators Technique: fundamentals and examples” by Alaus et al. presents the common operator technique for parametrization which is less standards dependent than the more conventional Common Function technique. The direct digitization of the radio frequency (RF) signal requires very high speed ADCs which is not readily available using current technology. Therefore, current SDR implementations typically down-converts the RF A. P. Vinod (*) School of Computer Engineering, Nanyang Technological University, Nanyang, Singapore e-mail: asvinod@ntu.edu.sg

Increasing device parameter variations in nanometer CMOS technologies cause large spread in circuit parameters such as delay and power, leading to parametric yield loss. For digital signal processing (DSP) hardware, variations in circuit parameters can significantly affect the quality of service (QoS). Existing post-silicon calibration and repair approaches rely on adaptation of circuit operating parameters such as voltage, frequency, or body bias and typically incur large delay or power overhead. This paper presents a novel low-overhead approach of healing DSP chips by commensurately truncating the operand width based on their process shifts. The proposed approach exploits the fact that critical timing paths in typical DSP datapaths originate from the least significant bits. Hence, truncation of these bits, by setting them at constant values, can effectively reduce the delay of a unit, thereby avoiding delay failures. The proposed technique is applied to two common DSP blocks, namely discrete cosine transform (DCT) and finite impulse response (FIR) filter. Simulation results show significant reduction in critical path delay along with a graceful degradation in the QoS. They also show large improvement in manufacturing yield (41.6%) with up to 5X savings in power compared to existing approaches such as voltage scaling and body biasing.

Nowadays the need for dealing with ultra-high speed Analog to Digital Converter (ADC) is becoming more and more common, from Telecommunications to Precise Instrumentation, every application is increasing the analog to digital interface data rate. The ultra-high sampling rate of the ADCs demands the use of advanced acquisition techniques as well as the latest technology available. The utilization of dedicated Application Specific Integrated Circuit (ASIC) is an expensive solution to deal with the very high throughput from the ADC and its lack of flexibility is a huge drawback. On the other hand, the technology, the architecture and the state-of-the art of the current Field Programmable Gate Arrays (FPGAs) make them especially suitable to act as interface between an ultra-high speed ADC and a data processing unit. Another extra advantage is the reconfigurability of the FPGAs, they can be quickly adapted to different ADCs or different data processing units. The purpose of this paper is to present a practical approach to interface an ultra-high speed 8-bit ADC, MAX104, from Maxim Integrated Circuit, which performs digitalization of the input signal with a sampling rate of 1Gsps and a commercial and popular FPGA, the Virtex2 Pro, from Xilinx Corporation. Once the ADC digital data have been acquired, then they can be processed by either the dedicated FPGA Digital Signal Processing (DSP) blocks, or the FPGA embedded processors or just send the data out to a PC for later processing. Hence, the proposed method of implementation can be used as front-end of a wide range of applications.

Manning Applied Technology is developing a series of compact and rugged interferometers with many applications, including chemical and biological agent detection. A nutating prism interferometer features high throughput, very rapid-scan capability and resistance to vibration. A novel multiplex Fabry-Perot interferometric spectrometer is especially compact and efficient, transferring about twice the modulated optical power to a detector, compared to a Michelson interferometer of equal volume. The bilithic interferometer features high throughput, intrinsic tilt compensation and compact size with the potential for high resolution measurements. For all of these interferometer geometries, digital signal processing (DSP) hardware and software are used to enhance the performance and allow rapid processing of data, including chemometric discrimination. Enhancements to system performance provided by DSP include application of Brault's data processing approach, frequency stabilization of a miniature solid state reference laser and computational correction of tilt errors. A key advantage of the DSP enhancements is compensation for non-ideal behavior of optical hardware. Many of the novel instruments described herein employ intrinsic optic tilt compensation. Either type of tilt compensation provides greater photometric accuracy and stability. Preliminary NESR characterization is reported for two of the instruments.

High-performance analog to digital converters (ADCs) require low-jitter clocks in order to obtain high resolutions (above 12 effective bits) at high-speed operation frequencies (input frequency higher than 80MHz). In these ultra-low-jitter applications, clock driver circuits consider multi-stage architectures usually comprised by a front-end differential amplifier, and a differential-to-single (D2S) conversion in voltage mode, followed by an output digital buffer. This paper proposes an alternative to perform the D2S operation in current mode as a way to optimize the trade-offs between power consumption and output jitter. Different clock driver circuit topologies with ultra-low-jitter specifications (< 200fs) are introduced and compared in a 0.18µm commercial CMOS process.

With the development of information technology, analog-to-digital converter (ADC) is widely used. In products such as radar, ultra wideband communication system, high-performance digital oscilloscope and so on, the speed performance of analog-to-digital converter is usually the bottleneck of the whole system performance, so the research of high-speed ADC has attracted much attention. ADC is an interface circuit that converts analog signals into digital signals that can be processed by DSP. This paper will start with the basic knowledge of ADC, explain the general working process of ADC, introduce several architectures and working principles suitable for high-speed ADC, and compare and analyze their advantages and disadvantages.

Digital signal processing (DSP) has been widely applied in optical communication systems to mitigate various signal distortions and has become one of the key technologies that have sustained data traffic growth over the past decade. However, the strict energy budget of application-specific integrated circuit-based DSP chips has prevented the deployment of some powerful but computationally costly DSP algorithms in real applications. As a result, fiber nonlinearity-induced signal distortions impede fiber communication systems, especially in wavelength-division multiplexed (WDM) transmission systems. To solve these challenges in DSP, there has been a surge of interest in implementing neural networks-based signal processing using photonics hardware (i.e., photonic neural networks). Photonic neural networks promise to break performance limitations in electronics and gain advantages in bandwidth, latency, and power consumption in solving intellectual tasks that are unreachable by conventional digital electronic platforms. This work proposes a photonic recurrent neural network (RNN) capable of simultaneously resolving dispersion and both intra and inter-channel fiber nonlinearities in multiple WDM channels in the photonic domain, for the first time to our best knowledge. Furthermore, our photonic RNN can directly process optical WDM signals in the photonic domain, avoiding prohibitive energy consumption and speed overhead in analog to digital converters (ADCs). Our proposed photonic RNN is fully compatible with mature silicon photonic fabrications. We demonstrate in simulation that our photonic RNN can process multiple WDM channels simultaneously and achieve a reduced bit error rate compared to typical DSP algorithms for all WDM channels in a pulse-amplitude modulation 4-level (PAM4) transmission system, thanks to its unique capability to address inter-channel fiber nonlinearities. In addition to signal quality performance, the proposed system also promises to significantly reduce the power consumption and the latency compared to the state-of-the-art DSP chips, according to our power and latency analysis.

Nowadays, there are is an increasing need for multimedia communication standards offering multi-access services and high data rates. Downscaling of integrated circuit technologies has made efficient and cost-effective digital signal processing (DSP) hardware possible in many modern wireless communication systems. This trend has contributed in the development of reconfigurable and flexible radio frequency (RF) systems in order to push the analog-to-digital interface close to the antenna by facilitating DSP.

The capability of a directly modulated laser (DML) can be dramatically enhanced through precise control of the drive current waveform based on digital signal processing (DSP) and a digital-to-analog convertor (DAC). In this paper, a novel method to pre-compensate fiber dispersion for metro and regional networks is described for a bit rate of 10.709 Gb/s using a DML. A look-up table (LUT) for the drive current is optimized for dispersion mitigation. The entries of the LUT are determined based on the effects of the DML adiabatic and transient chirp on pulse propagation, the nonlinear mapping between the input current and the output optical power, and the bandwidth of the DML package. A DAC operating at 2 samples per bit (21.418 GSa/s with 6 bit resolution) converts the digital samples at the output of the LUT to an analog current waveform driving the DML. Experimental results for a bit rate of 10.709 Gb/s and on-off keying demonstrate a transmission reach of 252 km using a DML intended for 2.5 Gb/s operation and 608 km using a chirp managed laser intended for 10 Gb/s operation. Using this approach (DSP + DAC), the generation of 10.709 Gb/s differential phase shift keying (DPSK) and 56 Gb/s 16-ary quadrature amplitude modulation, sub-carrier multiplexed (QAM SCM) optical signals using the direct modulation of a passive feedback laser is also presented. 6-bit DACs operating at sampling rates of 21.418 GSa/s and 28 GSa/s, respectively, was used to generate the requisite analog current waveform.