VLSI implementation of ternary gates using Tanner Tool

Over the last few decades, CMOS-based digital circuits have been steadily developed. However, because of the power density limits, device scaling may soon come to an end, and new approaches for circuit designs are required. Multi-valued logic (MVL) is one of the new approaches, which increases the radix for computation to lower the complexity of the circuit. For the MVL implementation, ternary logic circuit designs have been proposed previously, though they could not show advantages over binary logic, because of unoptimized synthesis techniques. In this paper, we propose a methodology to design ternary gates by modeling pull-up and pull-down operations of the gates. Our proposed methodology makes it possible to synthesize ternary gates with a minimum number of transistors. From HSPICE simulation results, our ternary designs show significant power-delay product reductions; 49 % in the ternary full adder and 62 % in the ternary multiplier compared to the existing methodology. We have also compared the number of transistors in CMOS-based binary logic circuits and ternary device-based logic circuits.

Traditional digital circuits use binary logic for implementation which requires more number of data lines to carry information. In contrast to binary, multiple-valued logic (MVL), digital circuits require less number of data lines to represent information. MVL uses more than two levels to represent a number; thereby reducing the number of interconnects. One of its kind is ternary logic, (known as radix-3 system) and uses three different voltage levels, whereas the other quaternary logic (radix-4 system) uses four different voltage levels to represent a number. Various digital circuits are implemented using MVL which potentially reduces the chip area, power consumption, and propagation delay. This article discusses about fundamental concepts of ternary, quaternary system and reviews some of arithmetic and logic circuits using ternary and quaternary logic. This paper also presents different methodologies used to implement arithmetic and logic operations using MVL. It is found that, due to the effective utilization of interconnects, MVL digital circuits provide better performance over binary digital circuits in terms of area, power, and delay.KeywordsNumber systemArithmetic and Logic circuitsChip areaMultiple-Valued Logic (MVL)Quaternary logicTernary logicTiming delayVLSI

The article proposes a method for synthesizing ternary binary logic functions using a multi-threshold element, which significantly extends the capabilities of ternary logic compared to traditional binary logic. The aim of the work is to develop an algorithm for synthesizing ternary logic functions, based on the use of a multi-threshold element, which simplifies the design of logical circuits and reduces energy consumption while maintaining high data processing speed. The study includes a comparative analysis of ternary and binary logic functions, allowing an assessment of the advantages of ternary logic, particularly its ability to process more values than binary logic, which opens up new possibilities for creating more efficient computing devices. Specifically, ternary logic can reduce the complexity of circuits and hardware resource usage, while also enhancing performance in tasks where energy efficiency is critical. An essential part of the research is the development of an algorithm for synthesizing ternary binary logic functions based on a four-threshold multi-valued element. Furthermore, a software module was implemented to automate the synthesis of ternary functions. The program not only generates a graphical representation of the logical circuit but also formulates the analytical expression corresponding to the given logical function. This significantly simplifies the design and analysis of logical systems and enhances the efficiency of computations. Considering the high potential of ternary logic, the results of this work are significant not only for theoretical research but also for practical applications in the development of new computing devices and technologies. The further development of these ideas could contribute to the progress in computational systems working on new principles and open up new possibilities for optimizing technological processes in various fields of science and engineering.

Many-valued logics in general and 3-valued logic in particular is an old subject which had its beginning in the work of Łukasiewicz [Łuk]. Recently there is a revived interest in this topic, both for its own sake (see, for example, [Ho]), and also because of its potential applications in several areas of computer science, such as proving correctness of programs [Jo], knowledge bases [CP] and artificial intelligence [Tu]. There are, however, a huge number of 3-valued systems which logicians have studied throughout the years. The motivation behind them and their properties are not always clear, and their proof theory is frequently not well developed. This state of affairs makes both the use of 3-valued logics and doing fruitful research on them rather difficult.Our first goal in this work is, accordingly, to identify and characterize a class of 3-valued logics which might be called natural. For this we use the general framework for characterizing and investigating logics which we have developed in [Av1]. Not many 3-valued logics appear as natural within this framework, but it turns out that those that do include some of the best known ones. These include the 3-valued logics of Łukasiewicz, Kleene and Sobociński, the logic LPF used in the VDM project, the logic RM3 from the relevance family and the paraconsistent 3-valued logic of [dCA]. Our presentation provides justifications for the introduction of certain connectives in these logics which are often regarded as ad hoc. It also shows that they are all closely related to each other. It is shown, for example, that Łukasiewicz 3-valued logic and RM3 (the strongest logic in the family of relevance logics) are in a strong sense dual to each other, and that both are derivable by the same general construction from, respectively, Kleene 3-valued logic and the 3-valued paraconsistent logic.

In terms of memory, multivalued logic can be the fitting logic for the existing binary logic. Ternary logic contains three symbols in place of two symbols used in the binary logic, i.e., 0, 1, 2. More information can be stored with the help of these three symbols. SRAM cell is widely used in the digital circuit. The SRAM cell designed using the ternary logic can be used in the design of large memory arrays designed using ternary logic. The traditional ternary inverter which is used in the design of the traditional ternary SRAM cell is unable to store the proper values for the second state, there is a voltage level drop, which in turn affects the data read/write value of the SRAM cell designed using this traditional ternary inverter. Hence there is a need to design the ternary inverter cell which can give the proper output voltage level of all three states of the ternary logic. The level shift ternary inverter is designed to fulfill this disadvantage. The ternary inverter is designed in order to achieve the ideal DC characteristics, and the same level shift ternary inverter is used in the design of level shift ternary SRAM. This ternary SRAM stores the data properly at read/write signal. The traditional ternary inverter and traditional ternary SRAM, level shift ternary inverter and level shift ternary SRAM are implemented in Cadence 45 nm technology. The traditional ternary inverter consumes 2.37 μW power, and the level shift ternary SRAM consumes 2.43 μW power. The traditional ternary SRAM consumes 3.012 μW and level shift ternary SRAM consumes 3.14 μW. At the cost of a little bit increased power and the number of transistors, the traditional ternary SRAM can be replaced with level shift ternary SRAM. This level shift ternary SRAM stores all the voltage levels at all three levels. The same level shift ternary SRAM cell can be used for the design of large memory arrays.

Multi-valued logic (MVL) is that logic which has two or more logic values. In complex digital circuits, MVL (mainly Ternary logic) offers several advantages over binary logic. Carbon Nanotube Field Effect Transistor (CNTFET) technology is ideal to implement ternary logic circuits because of the threshold voltage of CNTFETs depends on the physical dimensions (chirality) of their channel. This work presents the implementation of a three-bit Ternary Prefix Adder using CNTFET technology. In this paper, a carry propagate-generate concept is used in order to implement the ternary prefix adder. A Kogge-Stone based prefix network is preferred for carry computation due to its high performance. A low power enoder is used for reducing the overall power of the adder. HSpice tool is chosen for designing this system. Simulation results show that there is a significant reduction in Power Delay Product (PDP) by 28 % compared to all other previous works.

Background: Multiple-Valued Logic (MVL) is the non-binary-valued system, in which more than two levels of information content are available, i.e., L>2. In modern technologies, the dual level binary logic circuits have normally been used. However, these suffer from several significant issues such as the interconnection considerations including the parasitics, area and power dissipation. The MVL circuits have been proved to be consisting of reduced circuitry and increased efficiency in terms of higher utilization of the circuit resources through multiple levels of voltage. Innumerable algorithms have been developed for designing such MVL circuits. Extended form is one of the algebraic techniques used in designing these MVL circuits. Voltage mode design has also been employed for constructing various types of MVL circuits. Novelty: This paper proposes a novel MVLTRANS inverter, designed using conventional CMOS and pass transistor logic based MVLPTL inverter. Binary to MVL Converter/Encoder and MVL to binary Decoder/Converter are also presented in the paper. In addition to the proposed decoder circuit, a 4-bit novel MVL Binary decoder circuit is also proposed. Tools Used: All these circuits are designed, implemented and verified using Cadence® Virtuoso tools using 180 nm technology library.

The project presents the design of high performance quaternary Combinational circuits for lower power dissipation. Most of the digital electronic systems are based on the binary logic design which is limited by the requirement of interconnections which increases the chip area. The solution to this problem can be achieved using multi valued logic (MVL)/Quaternary logic. Most of the authors used methods which required Quaternary to Binary and Binary to Quaternary conversion for any arithmetic and logic operation and achieved satisfactory performances. Our aim is to develop MVL/Quaternary logic for combinational circuits under case study without converting these levels into binary logic and vice-versa. It will reduce one additional step, and improve the performance offering less chip size, saving more power. The design is targeted for 0.18um CMOS technology and the design tool for simulation will be Advanced Design System tool (ADS).

The increasing market of portable electronics devices and battery powered portable electronic systems is making a pressure to the whole chip design industry to reduce the power dissipation of the electronics circuits so that battery backup can be increased. CMOS SRAM memory consumes almost 55% power of the total digital circuit. It is also said that memories are the power hungry devices in any digital system but today no digital system can be completed without memories. This article is based on the motivation of reduction of the dynamic power in SRAM memory and focuses on the analysis in terms of power dissipation, delay and area of the 7-transistor SRAM memory cell at 90 nm technologies by using the Tanner tool. The article targets towards short circuit power dissipation as well as switching power dissipation. The circuit is characterized by using the 90 nm technology which is having a supply voltage of 1.0 volts and threshold voltage is 0.3 volts.

Tremendous amounts of data are being generated and should be processed during the massive employment of artificial intelligence and edge/cloud computing, necessitating computers with higher capabilities. However, as Moore's Law approaches its limit, enhancing computing capability through transistor miniaturization is becoming less feasible. New strategies for “more-than-Moore” are highly preferred to drive future technological advancements. Multiple-valued logic, especially ternary logic with its superior data density compared to traditional binary logic, offers a viable route to augment computing capability while reducing chip interconnections and dynamic power consumption. Despite the growing interest in ternary logic within academia and industry, its practical application remains limited due to the increased transistor count and connections required by earlier logic gate implementations. In this thesis, we present efficient implementation methods of basic ternary logic gates based on emerging nano-electronics including two-dimensional material-based transistors. The fabricated ternary devices show high performance in DC gain and low power consumption. Additionally, compact models of the devices have been established and calibrated, facilitating the circuit design and simulation in Electronic Design Automation (EDA) tools. At the circuit level, this thesis introduces novel ternary arithmetic circuits, including adders and multipliers, that are optimized for low power consumption and minimal delay. Finally, we showcase the practical benefits of ternary logic systems in data processing through the implementation of carry-free arithmetic circuits, underscoring their potential as a transformative computing paradigm.

Reversible quantum computer system is one of the best choices for future computer systems. Multiple-valued logic especially ternary logic is a good candidate for the realization of reversible quantum computer. An efficient logic synthesis mechanism is essential for the low-cost realization. Toffoli gate is an important gate for quantum logic synthesis. It is the basic element for the Galois Field Sum of Product (GFSOP) expression based logic synthesis mechanism. So, for low-cost realization of any ternary logic function, a low-cost implementation of Toffoli gate is very necessary. This paper shows a low-cost, practically realizable, and efficient realization of 3-qutrit ternary Toffoli gate by using ion-trap realizable Muthukrishnan-Stroud gate. This realization is more efficient and less costly than other realizations.

Implementing logic within memristive crossbar is an attractive approach to overcome the memory wall in conventional von Neumann architectures. Ternary logic with three logic levels can reduce the number of logic operations and enhance the computing speed compared to the binary logic. In this paper, a ternary logic-in-memory scheme is proposed based on the memristive dual-crossbar structure where the inputs and outputs are represented by the multi-level cells of memristors. Two inter-crossbar ternary logic gates and one intra-crossbar binary logic gate for both row and column-wise operations are supported in the proposed scheme to effectively reduce the operation latency. Experimental results show that the operation steps of the proposed multi-trit ternary adder are reduced by up to 83.82%, as compared with previously published binary memristive logic designs. The computation energy consumed by the proposed ternary adder is also reduced by up to 35.87% as compared to previously published binary IMPLY logic design.

In this scientific paper, a software library for Ternary logic gates will be built based on VHDL language to be used in the implementation of combinational Ternary logic circuits. The VHDL language had been designed to be used to automate and design Binary electronic logic systems. Therefore, several problems have been arised in adapting the VHDL language to be used with Ternary electronic logic systems. However, these problems have been solved and the result were encouragement to continue the study with the other Ternary components, so that a complete software library based on VHDL language for different Ternary components will be used as a tool in the design and simulation of Ternary electronic logic circuits and systems. 
 Keywords: Ternary logic, Ternary logic gates, VHDL language.

Multiple valued logic (MVL) is sought for designing high complexity, highly compact, parallel digital circuits. However, the practical realization of an MVL-based system is dependent on optimization of cost, which directly affects the optical setup. We propose a minimization technique for MVL logic optimization based on graphical visualization, such as a Karnaugh map. The proposed method is utilized to solve signed-digit binary and trinary logic minimization problems. The usefulness of the minimization technique is demonstrated for the optical implementation of MVL circuits.

The recent advancements in multivalued logic gates represent a rapid paradigm shift in semiconductor technology toward a new era of hyper Moore's law. Particularly, the significant evolution of materials is guiding multivalued logic systems toward a breakthrough gradually, whereby they are transcending the limits of conventional binary logic systems in terms of all the essential figures of merit, i.e., power dissipation, operating speed, circuit complexity, and, of course, the level of the integration. In this review, recent advances in the field of multivalued logic gates based on emerging materials to provide a comprehensive guideline for possible future research directions are reviewed. First, an overview of the design criteria and figures of merit for multivalued logic gates is presented, and then advancements in various emerging nanostructured materials—ranging from 0D quantum dots to multidimensional heterostructures—are summarized and these materials in terms of device design criteria are assessed. The current technological challenges and prospects of multivalued logic devices are also addressed and major research trends are elucidated.