Memory Address Research Articles (Page 2)

The boom in the digital communication, e-commerce and cloud-based systems has highlighted the nature of cryptographic systems in the ensuring of security in information exchange. Symmetric and asymmetric encryption algorithms belong to the most studied cryptographic paradigms and the building blocks of the existing security systems. Although both types provide the same degree of confidentiality the performance features of the two types and their actual performance is very different. The present paper will provide a comparison of the two kinds of algorithms with a focus on the computational speed, memory requirement, scalability, and attack resistance. The experimental findings and literature have demonstrated that the symmetry algorithms such as Advanced Encryption Standard (AES) is more efficient and quick in its simultaneous performance and must be applied in the case of encrypting huge amounts of information. On the other hand, asymmetric algorithms, including the Rivest Shamir Adleman (RSA) and Elliptic Curve Cryptography (ECC) are computationally inefficient, yet offer advantages in distributing keys, as well as authentication. These findings are the reason why there is an ever-growing tendency to consider hybrid cryptosystems incorporating the strengths of both approaches to reach an equilibrium of performance and security (Stallings, 2017; Singh and Kumar, 2020).

The deceleration of Moore's law and the energy-latency drawbacks of the von Neumann bottleneck have heightened the pursuit for beyond‑CMOS designs that integrate memory and compute. Self‑rectifying memristors (SRMs) have emerged as promising building blocks for high‑performance, low‑power systems by combining resistive switching with intrinsic diode-like behavior. Their unidirectional conduction inhibits sneak‑path currents in crossbar arrays devoid of external selectors, while nonlinear I-V characteristics, adjustable conductance states, low operating voltages, and rapid switching facilitate efficient vector-matrix operations, neuromorphic plasticity, and hardware security primitives. This review synthesizes the working mechanisms of SRMs, surveys material, and structural strategies and compares device metrics relevant to array‑scale deployment (rectification ratio, nonlinearity, endurance, retention, variability, and operating voltage). We assess SRM-enabled in-memory computing and neuromorphic applications, as well as security functions such as physical unclonable functions and reconfigurable cryptographic primitives. Integration pathways toward CMOS compatibility are analyzed, including back-end-of-line thermal budgets, uniformity, write disturb mitigation, and reliability. Finally, we outline key challenges and opportunities: materials/architecture co‑design, precision analog training, stochasticity control/exploitation, 3D stacking, and standardized benchmarking that can accelerate large‑scale SRM adoption. Through the use of specialized materials and structural optimization, SRMs are set to provide selector‑free, densely integrated, and energy‑efficient hardware for future information processing.

Memristor-based technologies are pivotal for advancing in-memory computing and neuromorphic systems, addressing the von Neumann bottleneck by enabling low-power, high-density data storage. This study investigates the resistive switching (RS) behavior of p-type CuO nanowires (NWs) synthesized via thermal oxidation of a Cu foam integrated with Ag (active) and Au (inert) electrodes. In situ transmission electron microscopy (TEM) and scanning TEM (STEM) reveal the dynamic formation and dissolution of Ag-based conductive filaments under an electrical bias, driven by electrochemical metallization (ECM). The CuO NWs exhibit unique axial planar defects that facilitate Ag+ ion migration and nucleation, enhancing RS performance. Electrical measurements demonstrate volatile and nonvolatile switching transitions modulated by compliance current, with asymmetric Ag/CuO NW/Au devices showing diode-like behavior due to Schottky barrier modulation. Conduction mechanisms, including Schottky emission, space-charge-limited current, and Poole-Frenkel emission, are elucidated, transitioning to ohmic conduction in the low-resistance state. These findings provide critical insights into defect-mediated filament dynamics and electrode-dependent RS mechanisms, advancing the development of CuO NW-based memristors for next-generation neuromorphic computing applications.

Deep learning architectures are increasingly limited by the memory wall — the “von Neumann bottleneck” that forces frequent data transfers between memory and processing units, throttling throughput and energy efficiency. To alleviate this bottleneck, researchers have explored Compute-in-Memory (CiM) architectures to accelerate the core computing primitives such as the matrix–vector multiplications (MVMs), within memory arrays. Yet, large language models based on transformers also require many non-linear softmax operations, creating a new bottleneck. From a technology perspective, non-volatile STT-MRAMs are promising for CiM thanks to their endurance, nonvolatility, and area footprint. However, conventional 1T–1R STT-MRAM CiM arrays place bit-cells in parallel, yielding lower MVM energy efficiency than 8T-SRAM CiM due to low device resistance; line parasitics and low OFF/ON ratios of STT-MRAM devices further limit row parallelism and scalability. In this context, we propose ROSETTA, a CiM array based on 3T–2R STT-MRAM bit-cells that uses series-resistance sensing and time-to-digital conversion (TDC) for low-power MVMs. An added word line also stores a ROM bit, enabling in-array tables for fast softmax, without increasing bit-cell area. We introduce a novel palindromic encoding of inputs and weights to mitigate the data-dependent nonlinearity in STT-MRAM CiM arrays based on TDC sensing. This enables 8× higher row-level parallelism than standard 1T–1R MRAM CiM and facilitates scaling to larger CiM arrays. Our macro occupies ∼ 47% less area and consumes 3.1× less MVM energy than an equivalent ROM-overlaid 8T-SRAM macro, at similar latency and accuracy. At the system level, a spatial architecture comprising our macros exhibits 11.7−14.5× and 1.44 − 1.5× higher energy efficiency than equivalent architectures comprising 1T-1R MRAM and 8T-SRAM ROM-overlaid CiM macros, respectively.

Matrix inversion in massive multiple-input multiple-output (MIMO) precoding imposes significant burden on the energy efficiency and processing latency of baseband units. In this paper, we first propose a memristor crossbar based in-memory computing circuit capable of supporting both zero-forcing (ZF) and minimum mean square error (MMSE) precoding. The circuit features a reduced matrix size and enables faster one-step computation without the need for timing control. Secondly, to address the computational inaccuracy caused by the limited conductance range of memristors, we develop an optimized matrix-to-conductance mapping scheme that jointly considers device physical constraints and matrix statistics, achieving over 60% reduction in relative computation error compared with baseline scheme. An associated lightweight circuit enhancement ensures compatibility with practical crossbar architectures, without incurring significant hardware overhead. Thirdly, we establish a memristor programming time model grounded in device-level potentiation and depression dynamics. The analysis yields closed-form expressions for the expected programming time and its upper bound, and is further validated through Monte Carlo simulations, enabling accurate estimation of the system throughput. Simulation results demonstrate that the proposed circuit achieves a bit error rate comparable to that of 64-bit floating-point precoding, while delivering over 100× improvement in both energy and area efficiency compared with the NVIDIA RTX A2000 graphics processing unit (GPU).

Designing computing-in-memory (CIM) chips with synaptic plasticity can potentially support energy-efficient on-chip learning in edge devices for rapid local task adaptation. Its silicon implementation is challenging as it requires hybridizing nonvolatile and volatile memory (VM) and customized computational operations. In this work, we propose a plastic CIM (P-CIM) macro featuring: 1) the logic-compatible flash (LF) cells in a standard 14-nm logic process that can be integrated with static random access memory (SRAM) cells in the same array; 2) the plastic cell array (PCA) that can perform matrix elementwise multiplication (MEM) followed by matrix-vector multiplication (MVM) in a single clock cycle; 3) the differential merged-into-array analog-to-digital converter (DMA-ADC) with capacitor reuse and a multielement sparsity-aware (MESA) scheme to reduce area and power consumption. A P-CIM macro integrating 32 k LF cells, 4 k SRAM cells, and 32 8-bit DMA-ADCs is fabricated in a 14-nm FinFET logic process. It achieves a peak energy efficiency (EF) of 22.64 TOPS/W for the MEM-MVM operations. It achieves computing accuracies of 78.04% on the Omniglot one-shot learning task and 89.65% on the CIFAR-10 pattern memorization task.

Ground roll is a dominant coherent noise in land seismic data, characterized by low frequency, low velocity, and high amplitude. often overlaps with reflection arrivals, thereby reducing the reliability of seismic imaging and interpretation. Existing deep learning approaches exhibit inherent limitations in ground-roll attenuation, since Convolutional Neural Network-based models are constrained by local receptive fields, while standard Transformer architectures require large training datasets and incur substantial computational and memory costs due to their global self-attention mechanism. In this study, we propose a U-shaped Swin Transformer (U-Swin Transformer) for ground-roll attenuation. The proposed model replaces global self-attention with window-based self-attention, achieving linear computational complexity with respect to the input size and thereby significantly improving efficiency and scalability. Two near-surface field datasets acquired from the inland sabkha of Jayb Uwayyid (SJUW) in the Saudi Kingdom and the coastal sabkha of Abu Dhabi (CSAD) are used to evaluate the method under realistic geological conditions. Experimental results demonstrate that the proposed U-Swin Transformer effectively handles aliased ground roll and signal-noise overlap, which remain challenging for the U-shaped neural network (U-Net) and F-K filtering. Although the denoising performance of the U-Swin Transformer is comparable to that of the Vision Transformer (ViT) with similar mean absolute error, peak signal-to-noise ratio, and structural similarity index measure, it achieves this performance with significantly lower computational cost and GPU memory consumption. Furthermore, incorporating a transfer learning strategy enables efficient adaptation of the U-Swin Transformer across different sabkha seismic environments, substantially reducing training time compared to training the model from scratch.

Recently, integrating video foundation models and large language models to build a video understanding system can overcome the limitations of specific vision tasks. Yet, existing methods either employ complex spatial-temporal modules or rely heavily on additional perception models to extract temporal features for video understanding, performing well only on short videos. For long videos, the computational complexity and memory costs associated with long-term temporal connections are significantly increased, posing additional challenges. Leveraging the hierarchical memory structure of the Atkinson-Shiffrin memory model, with tokens in Transformers being employed as the carriers of memory in combination, we propose MovieChat within a training-free memory consolidation mechanism to overcome these challenges, which transfers dense frames from short-term memory into sparse tokens in long-term memory by temporally merging adjacent frames. We lift pre-trained large multi-modal models for understanding long videos without additional trainable modules, employing a zero-shot approach. Additionally, in our new version, MovieChat+, we design an enhanced training-free vision-question matching-based memory consolidation mechanism to better anchor predictions to relevant visual content. MovieChat achieves state-of-the-art performance in long video understanding, along with the released MovieChat-1 K benchmark with 1 K long video, 2 K temporal grounding labels, and 14 K manual annotations.

Detection of changes in heterogeneous remote sensing images is vital, especially in response to emergencies like earthquakes and floods. Current homogenous transformation-based change detection (CD) methods often suffer from high computation and memory costs, which are not friendly to edge-computation devices like onboard CD devices at satellites. To address this issue, this paper proposes a new lightweight CD method for heterogeneous remote sensing images that employs the online all-integer pruning (OAIP) training strategy to efficiently fine-tune the CD network using the current test data. The proposed CD network consists of two visual geometry group (VGG) subnetworks as the backbone architecture. In the OAIP-based training process, all the weights, gradients, and intermediate data are quantized to integers to speed up training and reduce memory usage, where the per-layer block exponentiation scaling scheme is utilized to reduce the computation errors of network parameters by dynamically adjusting the integer representation range. Second, an adaptive filter-level pruning method based on the L1-norm criterion is employed to further lighten the fine-tuning process of the CD network. Experimental results show that the proposed OAIP-based method attains similar detection performance (but with significantly reduced computation complexity and memory usage) in comparison with state-of-the-art CD methods.

In-memory computing shows great potential for data-intensive applications, with memristor-aided logic (MAGIC) being a key enabler. Efficient electronic design automation (EDA) tools are essential for implementing arbitrary Boolean functions in this paradigm. This paper presents a logic synthesis and verification framework for MAGIC-based in-memory computing, enabling the mapping of Boolean functions to memristor arrays, generation of micro-operations, and verification of results. To improve upon previous approaches, we introduce an area-aware mapping tool that optimizes the utilization of resistive random-access memory (RRAM). During logic synthesis, we propose a reinforcement learning (RL)-based tool for automatically generating optimized sequence flows, adapting to network characteristics for better mapping. To verify the mapping correctness, we introduce an equivalence verification tool that uses circuit structure for fast validation, also identifying bugs missed by previous methods. Experimental results show that our mapping tool reduces RRAM usage by 13% and 10% on average, with minimal increases of 1% and 2% in computation cycles, compared to state-of-the-art techniques. Additionally, the proposed synthesis recipe generation tool outperforms fixed flows and three heuristic algorithms (greedy, simulated annealing, and genetic algorithms), reducing the area-delay product by 21% and 6% for the ISCAS’85 and EPFL benchmarks, respectively.

We propose a novel ferroelectric field-effect transistor (FeFET)-based ternary content addressable memory (TCAM) that exploits the gate-induced drain leakage (GIDL) effect to achieve ambipolar functionality. This design introduces the first FeFET TCAM with symmetric source/drain ohmic contacts, delivering significant advantages in cell scalability and fabrication simplicity, thereby establishing a foundation for large-scale TCAM array integration. The device’s matching functionality was validated under both static and transient conditions, exhibiting a reliable noise margin and a current ratio of approximately 10, maintained after over <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times 10^{{3}}$</tex-math> </inline-formula> query cycles or <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10^{{4}}$</tex-math> </inline-formula> s of query delay. This strategy paves the way for the next generation of high-throughput, large-scale TCAM arrays.

Frank Stuart Dethridge Memorial Address: Admiralty Through the Looking Glass

This research paper investigates the adoptability of the multi-sliced 2D finite element method (FEM) on the skewed interior permanent magnet (IPM) motor. Conventional IPM motors are without skewing, and analyzed by using the 2D FEM, however, skewed IPM motors require 3D FEM, thus huge computation time and memory are needed. The multi-sliced 2D FEM consumes less computational time compared to a traditional 3D FEM. Therefore, a multi-sliced 2D FEM is presented and adopted to analyze the skewed-stator IPM motor for the hybrid electric vehicle (HEV) application. To realize the computational accuracy of the multi-sliced 2D FEM, the back EMF of a conventional un-skewed IPM motor computed by a conventional 2D FEM is compared with the back EMF results of the multi-sliced 2D FEM. The electromagnetic characteristics, such as cogging torque, torque ripples, back EMF and electromagnetic torque of the skewed-stator IPM motor are computed using the multi-sliced 2D FEM, and results are discussed.

Innovating electronic devices to mimic human brain behaviors has been a long-standing desire. (Mehonic, A., Kenyon, A. J. Brain-inspired computing needs a master plan. Nature 2022, 604, 255-260 and Mead, C. Neuromorphic electronic systems. Proceedings of the IEEE 1990, 78, 1629-1636). Here, we present a semi-floating body memory (SFBM) exhibiting various human brain-like memory behaviors. The SFBM is designed similarly to a p-type silicon-on-insulator (SOI) MOSFET, except that a metal/graphene/silicon overlapping heterojunction is formed close to the drain. The proper operation of device terminal bias voltages introduces and modulates the impact ionization (II) at the heterojunction interface and forms an ungated semi-floating body underneath for charge storage, further enabling multiple unique memory behaviors. The SFBM achieves a fresh retention time of ∼1 h, 300× that of the conventional floating body memory. Importantly, the retention time is extended to over a day by the read operation, precisely mimicking the revisitation behavior of human memory. In addition, the SFBM responds to a 20 ns write pulse in a few seconds, and it mimics the shocking behavior of the human brain in response to a very fast and strong stimulus.(Kim, J. J. & Fanselow, M. S. Modality-Specific Retrograde Amnesia of Fear. Science 1992, 256, 675-677 and Brewin, C. R. Memory and Forgetting. Current Psychiatry Reports 2018, 20, 87). Finally, the back gate control of the SFBM enables real-time quantification of the device current up to 4 orders of magnitude; this resembles the hormone regulation of synaptic weights in the human brain. All these brain-like features position the SFBM as a strong candidate for brain-inspired computing units, and a 1T-1S content-addressable memory (CAM) cell is experimentally demonstrated using a minimum number of transistors for future compute-in-memory (CIM) purposes.

ABSTRACT Accurate time series forecasting is a cornerstone of contemporary power and energy systems, supporting essential operational and planning functions including short‐term load prediction, electricity price forecasting and so on. Transformer‐based models achieve state‐of‐the‐art results by embedding series into tokens, but their quadratic time and space complexity limits the practical applications in real‐world scenarios. In this paper, we propose to chunk the tokens before feeding them to the encoder, in which attention calculations between tokens are limited to within the same chunk. Leveraging the frequency domain characteristics of the series, we employ locality sensitive hashing (LSH) techniques to ensure that series with similar frequency patterns are assigned to the same chunk. By fixing the chunk size, our method reduces the complexity of the transformer‐based model from to . Within each chunk, distilled features are concatenated to incorporate global information. Additionally, the running score update mechanism allows our framework to adapt the chunking strategy according to the data distribution. Extensive experiments demonstrate that, across multiple real‐world datasets and models, the proposed method maintains performance comparable to the original models while substantially reducing computational complexity and memory usage.

ABSTRACT Engineering semiconductor heterojunctions is a pivotal research frontier for developing next‐generation optoelectronic devices, particularly for neuromorphic computing. However, performing precise, stimulus‐selective control over interfacial carrier dynamics to unlock advanced memory and logic functions remains a significant challenge. Herein, we unveil a novel “photon‐energy‐gated selective carrier accumulation” mechanism within macroscopically ordered ZnO/Ga 2 O 3 core–shell nanowire heterojunctions, governed by the Type‐I band alignment at the heterointerface. This unique architecture, fabricated via a super‐aligned carbon nanotube template, not only boosts the UV photoresponsivity by 78‐fold compared to pure ZnO counterparts but also enables a remarkable wavelength‐selective activation of persistent photoconductivity. Harnessing this optically switchable memory effect, we demonstrate its application in optoelectronic synaptic devices, and we also prove its potential in physical reservoir computing system, achieving a high classification accuracy of 87.9% on the Fashion ‐ Modified National Institute of Standards and Technology (F‐MNIST) dataset. This study provides a new paradigm for designing intelligent optoelectronic devices by precisely manipulating interfacial carrier dynamics, opening promising avenues for in‐sensor computing and advanced photonic memory.

The increasing data rate has become a major issue confronting next-generation intracortical brain-machine interfaces (iBMIs). The scaling number of recording sites requires complex analog wiring and lead to huge digitization power consumption. Compressive event-based neural frontends have been used in high-density neural implants to support the simultaneous recording of more channels. Event-based frontends (EBF) convert recorded signals into asynchronous digital events via delta modulation and can inherently achieve considerable compression. But EBFs are prone to false events that do not correspond to neural and may affect the output firing rate, which is the key feature for neural decoding. Spike detection (SPD) is a key process in the iBMI pipeline to detect neural spikes and further reduce the data rate. However, conventional digital SPD suffers from the increasing buffer size and frequent memory access power, and conventional spike emphasizers are not compatible with EBFs. In this work we introduced an event-based spike detection (Ev-SPD) algorithm for scalable compressive EBFs. To implement the algorithm effectively, we proposed a novel low-power 10-T eDRAM-SRAM hybrid random-access memory (HRAM) in-memory computing (IMC) bitcell for event processing. We fabricated the proposed 1024-channel IMC SPD macro in a 65nm process and tested the macro with both synthetic dataset and Neuropixel recordings. The proposed macro achieved a high spike detection accuracy of 96.06% on a synthetic dataset and 95.08% similarity and 0.05 firing pattern MAE on Neuropixel recordings. Our event-based IMC SPD macro achieved a high per channel spike detection energy efficiency of 23.9 nW per channel and an area efficiency of 375 μm2 per channel. Our work presented a SPD scheme compatible with compressive EBFs for high-density iBMIs, achieving ultra-low power consumption with an IMC architecture while maintaining considerable accuracy.

Phase change materials (PCMs) have garnered significant attention due to their applications in phase change memory (PCM) technology, which has the potential to surpass the von Neumann bottleneck via in-memory computing. This is particularly useful in artificial intelligence applications requiring rapid data transfer. Therefore, identifying the bonding mechanism in such materials is crucial, as it will aid in designing better materials for PCM applications. In this context, a new bonding mechanism named metavalency, indicating a chemical bond in between metallic and covalent, was introduced recently to describe the bonding in phase change materials. Metavalent materials are characterized by nearly half bond order, large Born effective charge (BEC), low band gap, moderate electrical conductivity, and large optical dielectric constant. However, their bonding features overlap significantly with those of the well-known hypervalent and partial σ-bonded systems, raising fundamental questions about whether metavalency constitutes a truly distinct bonding mechanism. Here, we employ molecular orbital theory and DFT calculations to show that the known metavalent compounds are electron-sufficient/rich hypercoordinate systems with partial σ bonds formed mainly by p–p overlap and have low ionicity, low band gap, and consequently large BEC. This implies that they belong to a distinct class of compounds, though the bonding mechanism is not new. This refined understanding of metavalent bonding provides a foundational framework for the rational design of novel PCMs, paving the way for advancements in phase change memory technology.

Memristors have emerged as a promising technology for next-generation memory and neuromorphic computing. Anodization offers an attractive alternative fabrication method with a wide range of tunable parameters and easy production setups.

Ferroelectric capacitive memory (FeCAP) holds enormous potential for low-power, high-density in-memory computing. While hafnia-based FeCAPs have attracted attention for their silicon compatibility, they suffer from limited performance, such as a narrow memory window and relatively high switching fields. In this work, an FeCAP device is developed on the basis of a single-crystalline barium titanate (BTO) membrane, a perovskite oxide thin film that can be epitaxially lifted off and transferred onto a silicon platform. By engineering the device structure and epitaxy process, polarization asymmetry is introduced in capacitance-voltage characteristics. The resulting BTO-based FeCAP exhibits superior memory behavior, including a wide memory window of 308 picofarads and a low switching field of 0.005 megavolts per centimeter, outperforming conventional hafnia-based FeCAPs. Furthermore, these properties are preserved after active layer transfer onto a silicon platform. This approach provides a viable pathway for high-quality BTO to integrate into industry-compatible processes and to drive progress in future logic/memory applications.