memory address Research Articles (Page 6)

While neural networks (NNs) have achieved great results in various intelligent tasks like image classification and speech recognition, real-world scenarios have more applications beyond just NN processing like graph convolutional network (GCN) and deep-learning recommendation model (DLRM), which typically consist of sparse gathering (SpG) and sparse algebra (SpA). Their large application size leads to substantial data movement. Although the fusion of digital computing-in-memory (CIM) and multichip-module (MCM) can reduce data movement efficiently and scale out CIM’s capacity in a high-yield solution, the MCM-CIM system raises new challenges for beyond-NN acceleration: SpG involves repeated off-chip DRAM access, interchiplet access, and redundant reduction operations; SpA suffers from inter-CIM workload imbalance and intra-CIM under-utilization. Thus, we design TensorCIM as the CIM processor chiplet with three corresponding features: 1) the redundancy-eliminated gathering manager (REGM) dynamically maintains frequently accessed features and reduction results in the CIM to eliminate redundant accesses and reductions; 2) the equal operation-based CIM initializer (EOCI) calculates effective multiply-accumulation (MAC) operations and initializes CIM macros with a balanced inter-CIM workload at the subarray level; and 3) the input-lookahead CIM (ILA-CIM) architecture looks ahead at future inputs to fully utilize CIM logic. The fabricated MCM-CIM system consumes only 3.7 nJ/Gather for the GCN model, achieving 8.3-TFLOPS/W algebra efficiency at FP32.

This study aims to enhance the RC5 algorithm to improve encryption and decryption speeds in devices with limited power and memory resources. These resource-constrained applications, which range in size from wearables and smart cards to microscopic sensors, frequently function in settings where traditional cryptographic techniques because of their high computational overhead and memory requirements are impracticable. The Enhanced RC5 (ERC5) algorithm integrates the PKCS#7 padding method to effectively adapt to various data sizes. Empirical investigation reveals significant improvements in encryption speed with ERC5, ranging from 50.90% to 64.18% for audio files and 46.97% to 56.84% for image files, depending on file size. A substantial improvement of 59.90% is observed for data files sized at 1500000kb. Partitioning larger files notably reduces encryption time, while smaller files experience marginal benefits. Certain file types benefit from both strategies. Evaluation metrics include encryption execution time and throughput, consistently demonstrating ERC5's superiority over the original RC5. Moreover, ERC5 exhibits reduced power consumption and heightened throughput, highlighting its multifaceted benefits in resource-constrained environments. ERC5 is developed and tested on various file types and sizes to evaluate encryption speed, power consumption, and throughput. ERC5 significantly improves encryption speed across different file types and sizes, with notable gains for audio, image, and large data files. While partitioning smaller files only slightly improves encryption time, larger files partitioning yields faster results. Future research could explore ERC5 optimizations for different computing environments, its integration into real-time encryption scenarios, and its impact on other cryptographic operations and security protocols.

SrFeOx (SFO) offers a topotactic phase transformation between an insulating brownmillerite SrFeO2.5 (BM-SFO) phase and a conductive perovskite SrFeO3 (PV-SFO) phase, making it a competitive candidate for use in resistive memory and neuromorphic computing. However, most of existing SFO-based memristors are nonvolatile devices which struggle to achieve short-term synaptic plasticity (STP). To address this issue and realize STP, we propose to leverage ferroelectric polarization to effectively draw ions across the interface so that the PV-SFO conductive filaments (CFs) can be ruptured in absence of an external field. As a proof of concept, we fabricate ferroelectric Pb(Zr0.2Ti0.8)O3 (PZT)/BM-SFO bilayer films with Au top electrodes and SrRuO3 bottom electrodes. The device exhibits the desired volatile resistive switching behavior, with its low resistance state decaying over time. Such volatility is attributed to the positive polarization charge near the PZT/SFO interface, which can attract the oxygen ions from SFO to PZT and hence lead to the rupture of CFs. Moreover, this volatile device successfully emulates STP-related synaptic functions, including excitatory postsynaptic current, paired-pulse facilitation, learning-experience behavior, associative learning, and reservoir computing. Our study showcases an effective method for achieving volatile resistive switching and STP, which may be applied to various systems beyond SFO-based memristors.

Multi-object tracking (MOT) in satellite videos is a challenging task due to the small size and blurry features of objects, which often lead to intermittent detection and tracking instability. Many existing object detection and tracking models often struggle with these issues, as they are not designed to effectively handle the unique characteristics of satellite videos. To address these challenges, we propose LocaLock, a joint detection and tracking framework for MOT that incorporates feature matching concepts from single object tracking (SOT) to enhance tracking stability and reduce intermittent tracking results. Specifically, LocaLock utilizes an anchor-free detection backbone for efficiency and employs a local cost volume (LCV) module to perform precise feature matching in the local area. This provides valuable object priors to the detection head, enabling the model to “lock” onto objects with greater accuracy and mitigate the instability associated with small object detection. Additionally, the local computation within the LCV module ensures low computational complexity and memory usage. Furthermore, LocaLock incorporates a novel motion flow (MoF) module to accumulate and exploit temporal information, further enhancing feature robustness and consistency across frames. Rigorous evaluations on the VISO dataset demonstrate the superior performance of LocaLock, surpassing existing methods in tracking accuracy and precision within the demanding satellite video analysis domain. Notably, LocaLock achieved state-of-the-art performance on the VISO benchmark, achieving a multi-object tracking accuracy (MOTA) of 62.6 while ensuring fast running speed.

Encryption and decryption of data with very low latency and high energy efficiency is desirable in almost every application that deals with sensitive data. The advanced encryption standard (AES) is a widely adopted algorithm in symmetric key cryptography with numerous efficient implementations. Nonetheless, in scenarios involving extensive data processing, the primary limitations on performance and efficiency arise from data movement between memory and the processor, rather than data processing itself. In this article, we present a novel in-memory computing (IMC) approach for AES encryption and key-expansion, and experimentally validate it on an IMC prototype chip based on phase-change memory (PCM) technology. We leverage operators stored in PCM crossbar arrays to achieve the flexibility to tune performance at runtime based on the amount of free storage available in the memory system. In addition, we introduce a method for parallel in-memory polynomial modular multiplication and evaluate the potential of intrinsic stochastic properties of PCM devices for random key generation. We show how to further improve efficiency with minimal additional auxiliary circuitry. To evaluate the performance within a custom-built large-scale in-memory AES system, we design and implement a cycle-accurate simulator that integrates parameters from Spice simulations for detailed latency and energy consumption analysis of the AES algorithm. Our evaluations indicate that our IMC-based AES approach outperforms state-of-the-art methods, achieving speed factor improvements of up to 19.7 at equivalent energy efficiency.This article is part of the theme issue 'Emerging technologies for future secure computing platforms'.

The advent of in-memory computing has introduced a new paradigm of computation, which offers significant improvements in terms of latency and power consumption for emerging embedded AI accelerators. Nevertheless, the effect of the hardware variations and non-idealities of the emerging memory technologies may significantly compromise the accuracy of inferred neural networks and result in malfunctions in safety-critical applications. This article addresses the issue from three different perspectives. First, we describe the technology-related sources of these variations. Then, we propose an architectural-level mitigation strategy that involves the coordinated action of two checksum codes designed to detect and correct errors at runtime. Finally, we optimize the area and latency overhead of the proposed solution by using two accuracy-aware hardware-software co-design techniques. The results demonstrate higher efficiency in mitigating the accuracy degradation of multiple AI algorithms in the context of different technologies compared with state-of-the-art solutions and traditional techniques such as triple modular redundancy. Several configurations of our implementation recover more than 95% of the original accuracy with less than 40% of the area and less than 30% of latency overhead.This article is part of the themed issue 'Emerging technologies for future secure computing platforms'.

Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devices. Nonvolatile memory (NVM) devices offer one such attractive alternative with ∼2× density and data retention after powering off. Compute-in-memory (CIM) architectures further improve energy efficiency by fusing the computation operations with AI model storage. Electronic characteristics of NVM devices, like resistance in the two resistance states, directly affect the circuit designers' decisions and result in the varying performance of NVM-CIM chips. In this mini review, we assess the bounds on device resistances for accuracy and circuit performance to suggest recommendations to device engineers for frictionless device-circuit-system interactions. Furthermore, we review challenges in reliably programming NVM devices, followed by benchmarking recent NVM-CIM chips. Our literature review and analytical modeling reveal that a high resistance ratio and low variability are favored, and the resistance in a low resistance state is bound by accuracy and circuit performance constraints.

WANET is a network built in an ad hoc network where various connecting devices and moving wireless nodes make connection with the exchange valuable information and wireless medium to one another. As the size of the wireless networks and internet architectures are increasing, there is an exponential demand for data processing and sharing resources in the WANETs. Most of the traditional node authentication models in WANET’s require high computational memory and resource constraints for data security and node authentication. In order to overcome these problems in the traditional models, a novel non-linear integrity-based intrusion detection models is designed and implemented in WANETs. In this work, a hybrid security protocol is designed and developed for the node-to-node communication system. In the proposed security protocol, a hybrid integrity approach and encryption framework is implemented on N2N communication process. Experimental results show that the present security protocol has better improvement on different metrics over traditional security approaches.

Recent experimental studies in the awake brain have identified a rule for synaptic plasticity that is instrumental for the instantaneous creation of memory traces in area CA1 of the mammalian brain: Behavioral Time scale Synaptic Plasticity. This one-shot learning rule differs in five essential aspects from previously considered plasticity mechanisms. We introduce a transparent model for the core function of this learning rule and establish a theory that enables a principled understanding of the system of memory traces that it creates. Theoretical predictions and numerical simulations show that our model is able to create a functionally powerful content-addressable memory without the need for high-resolution synaptic weights. Furthermore, it reproduces the repulsion effect of human memory, whereby traces for similar memory items are pulled apart to enable differential downstream processing. Altogether, our results create a link between synaptic plasticity in area CA1 of the hippocampus and its network function. They also provide a promising approach for implementing content-addressable memory with on-chip learning capability in highly energy-efficient crossbar arrays of memristors.

Computing in memory (CIM), which alleviates the need to transfer a large amount of data between processor and memory, significantly reducing latency and energy consumption, is a promising new computing architecture for addressing the von Neumann bottleneck problem. This article proposes a CIM array structure composed of self-recycling 10T static random access memory (SRAM) cells, which can realize orthogonal data writing, and multiple Boolean logical operations for the entire array. The self-recycling and full-array activation characteristics are extremely suitable for accelerating diverse data processing algorithms such as the Advanced Encryption Standard (AES). A 4-kb SRAM is implemented in 55-nm CMOS technology to verify the effectiveness of the design. Compared with other state-of-the-art architectures, the throughput and the operating frequency of the proposed CIM macro are increased to 843 GOPS/kb (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.64\times $</tex-math> </inline-formula>) and 823.7 MHz (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.6\times $</tex-math> </inline-formula>), respectively. The energy efficiency reaches 246.9 TOPS/W. When applied to the AES, the energy consumption is 35.77% less than the digital CIM architecture that is not self-recycling.

Computing-in-Memory (CIM) has emerged as a promising paradigm to address the Von-Neumann bottleneck, demonstrating significant advantages in enhancing the energy efficiency of Deep Neural Networks (DNNs). However, its reliability is challenged by device variation and Stuck-at Faults (SAFs) in Non-Volatile Memories (NVMs). Conventional quantization methods do not adequately address the device variation issue in CIM, leading to substantial degradation in the inference accuracy using CIM architectures. To address these challenges, this work proposes a hybrid optimization framework tailored for CIM architectures, combining a Variation-and-Fault-Aware Canonical Signed Digit (VFA-CSD) quantization scheme and a Progressive Mapping Approach (PMA). Device non-idealities are modeled through normalized conductance and fault matrices. VFA-CSD effectively reduces quantization error caused by variation and faults, keeping error below 0.5 Least Significant Bit (LSB) under variation and reducing error by nearly 50% compared to binary weights under combined faults. PMA further enhances inference accuracy with minimal retraining. Experimental results show that at a 10% fault rate, 4-bit models suffer less than 2.5% accuracy loss across various datasets, while 8-bit models achieve accuracy nearly identical to pretrained baselines. These results demonstrate the robustness and efficiency of the proposed scheme for reliable CIM deployment.

Conceptual metaphors, which help conceptualizing one concept in terms of another (Lakoff &amp; Johnson [1980]), often migrate from a source scientific domain onto another. This article aims at describing the “interdomanial nomadism” (Rossi [2015]) of the conceptual metaphors associated with memory from computer science to quantum computing. One corpus of 35 texts about quantum computing was compiled from the Scientific American. This corpus is made of all the texts ever published in the magazine which contain the keywords “quantum computing” or “quantum computer(s)”. Another corpus of 15 texts about computer memory was compiled from the same magazine. The search for these texts was refined by looking for the keyword “computer memory” and excluding the keyword “quantum”. Our analysis relies on the extraction of terms related to memory in both corpora (more specifically on the terms that the corpora have in common) and on the identification of their metaphoricity to investigate any potential interdomanial shifts. First, we extracted the keywords from both corpora in Sketch Engine (Kilgarriff et al. [2014]). This extraction gave us a general idea of the conceptual metaphors of memory in both computer science and quantum computing. Then, we observed, through the means of similarity analysis, the words which co-occur the most with the word “memory” in a close context. This observation enabled us to have a further look at potential metaphorical expressions associated with memory. The MIPVU method (Metaphor Identification Procedure Vrije Universiteit Amsterdam) developed by Steen et al. [2010] was selected to identify metaphorical items in the corpora. The analysis of the keywords resulted in the identification of 9 conceptual metaphors used to describe memory, among which 4 are common to both corpora, providing first evidence of metaphorical nomadism of memory from computer science to quantum computing. Additionally, 5 types of nomadic patterns were identified based on the examples from the corpora, providing better insight into metaphor interdomanial nomadism.

This article presents an energy-harvester-powered ultra-low power (ULP) vibration-based condition monitoring (VbCM) chip with a digital compute-in-memory (CIM)-based deep neural network (DNN) accelerator. The VbCM chip achieves end-to-end signal processing, including a piezoelectric (PZ)-based accelerometer sensor and its readout circuit (RoC), a digital CIM-based DNN accelerator and a ULP radio system. To perform the targeted rotating bearing anomaly detection task with best-in-class accelerator power consumption and energy efficiency, the chip integrates several technologies from the algorithm level to the hardware level, including: 1) Compressing deep neural network (C-DNN) to reduce the network size through a feature compressor module (FCM); 2) Signal chain characteristic adaptation from direct training of the time-domain feature extractor (TD-FEx); 3) ULP 13T SRAM CIM bitcell to perform high energy efficiency in-cell multiplication; and 4) ripple counter (RCNT)-based accumulation scheme to improve the overall energy efficiency of the accelerator under a 0.35 V supply voltage. The VbCM chip achieves 90.7 nW total power with an inference FR of 20 frames/s, and the DNN accelerator’s energy efficiency achieves 18.8 fJ/MAC. With all the weight parameters statically stored in the CIM macros, the accelerator can operate with an inference accuracy of 91.3% while consuming 24.7 nW.

Compute-in-Memory (CIM) is an effective approach to boost the efficiency of AI hardware by reducing data movement. Digital CIM (DCIM) has garnered extensive attention owing to its immunity to PVT variations and high precision. Recently, a lookup table (LUT)-based DCIM architecture was proposed, which stores the precomputed summations of adjacent weights in memory, thereby alleviating the substantial overhead of adder trees in traditional DCIM designs. However, the efficiency of LUT-based DCIM is difficult to further improve due to the bit-serial input method and the power-hungry LUT readout operations. To address this challenge, this work presents a BooLUT-CIM design that integrates the advantages of LUT-based CIM and Booth algorithm, reducing the quantity of lookup and addition operations by a half. A LUT compression method derived from computation-friendly numerical relationships is utilized to reduce circuit overhead. Additionally, a negative magnitude-bits inversion storage scheme is proposed to reduce inefficient discharge, saving 38% of LUT array readout power on average. A prototype of this design is implemented in 28nm CMOS technology for validation. Simulation results show that the macro achieves an energy efficiency of 52.4 TOPS/W at 0.9V, 400 MHz, which is 1.3× higher than prior arts.

A review of correlated electron VO2-based memristors in neuromorphic circuitry towards memory computing and sensing applications.

Hyperdimensional computing (HDC) is emerging as an efficient and robust computing paradigm that has strong resilience to various types of errors. The error robustness nature of HDC makes it a good match for error-prone memory systems. However, the mechanisms behind HDCs robustness are not fully understood. In this work, we propose HyperMetric, a framework to train highly robust and hardware-friendly HDC models. We found that HDC’s error resilience is driven by Hamming distance margin between hypervectors. Based on this, we propose HyperMetric training that is based on metric learning in order to optimize for high robustness. The experiments show that HyperMetric trained HDC models deliver up to 17W larger Hamming distance margin and up to 14.3 We accelerate HyperMetric trained models using ReRAM. As compared to state-of-the-art HDC algorithms OnlineHD and HyDREA, HyperMetric ReRAM accelerator is > 20% more accurate for computing-in-memory (CIM) errors and > 10% more accurate for bit errors even in the face of variations. Furthermore, HyperMetric hardware is 35% more accurate in comparison with existing tinyHD and GENERIC accelerators in the face of 3× ReRAM resistance variance, and 20% more accurate with BER of up to 20% due to voltage scaling while keeping a good balance between area, power, and processing laten

Spiking Neural Networks (SNN) is well-suited for always-on near-sensor intelligence, due to its spike-driven nature; however, its IC realization is complicated by the temporal dimension. Asynchronous low-power SNN chips employing analog computing-in-memory (CIM) techniques have been demonstrated to enable real-time, energy-efficient inference. However, their tolerance to nonidealities remains to be improved, and their peripherals for multiphase or multilevel signal control are complex. This paper proposes a general-purpose, spike-driven SNN chip designed with efficient analog-computing circuits, featuring two key contributions: 1) A compact direct current-add CIM synapse design that significantly simplifies control peripherals, thereby reducing latency and enhancing energy efficiency. 2) A PVT-aware multi-network learning method underpinned by detailed analyses and modeling, coupled with a label-normalization-based synapse-strengthening method, to mitigate the impact of nonidealities. Fabricated in 65nm CMOS process, the proposed design achieves a state-of-the-art latency of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$10\mu $</tex-math> </inline-formula>s and an energy efficiency of 0.40pJ/spike. The generalization ability of the design is verified through its successful application to two distinct tasks: voice activity detection (VAD) and ECG anomaly detection. The tolerance to nonidealities is validated by the VAD task. The ten chips maintain over 90% detection accuracy across signal-to-noise ratios (SNRs) of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\sim 16$</tex-math> </inline-formula>dB, ±10% supply voltage variation, and a temperature range of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$- 25\sim 55^{\circ }$</tex-math> </inline-formula>C.

Abstract The safe and stable operation of modern power systems is inseparable from the electromagnetic calculations of their spatial environment. Focusing on the electrostatic field, this paper deduces the boundary integral equations of the conductors and dielectrics, constructs the boundary discrete matrix equations, and then adopts the characteristic basis function method (CBFM) to obtain the electrostatic response of the target bodies. In the process of constructing the basis functions, the adaptive cross approximation (ACA) algorithm is introduced, which can reduce the computational complexity and memory demand through the low grade decomposition of the impedance matrix, and further result in calculation efficiency improvement. Numerical examples of the 35 kV transmission tower and the solar photovoltaic power panel under the premise of the given boundary conditions verify the accuracy and efficiency of the proposed algorithm.

SOFIE is a fast Machine Learning inference engine developed at CERN, capable of translating trained deep learning models—provided in ONNX, Keras, or PyTorch formats—into C++ code for efficient inference. The generated code has minimal dependencies, making it easily integrable into the data processing and analysis workflows of high-energy physics (HEP) experiments. This study presents a comprehensive benchmark analysis of SOFIE against leading machine learning frameworks for model evaluation, including PyTorch, TensorFlow XLA, and ONNX Runtime. We focus on evaluating their performance in HEP applications, particularly for typical models such as Graph Neural Networks for jet tagging, and Variational Autoencoders and Generative Adversarial Networks for fast simulation. Our assessment considers key factors such as computational speed, memory usage, scalability, and ease of integration with existing HEP software ecosystems. Through this comparative study, we aim to provide insights that help the HEP community select the most suitable framework for their specific needs.

The express expansion of the Internet of Things (IoT) has led to an exponential increase for data being generated and transmitted from various connected devices. This poses significant challenges in terms of data privacy and security, as unauthorized access to such sensitive information can have severe consequences like identity theft or financial fraud. This research proposes a model for sensitive data detection and protection in IoT, based on deep learning and optimization-enabled secure encryption. By combining deep learning-based sensitive data detection and optimization-enabled secure encryption, this model offers a comprehensive solution to preserve data privacy in IoT. The proposed model uses a novel and secure encryption algorithm, ensuring the privacy of the data. An algorithm, Improved Skill Optimization Algorithm (ISOA), which enhances the performance of existing optimization algorithms by incorporating the concept of Double Exponential Smoothing (DES), is proposed for the secure key generation for the data encryption. Data Encryption Standard (DES) is a block cipher algorithm that encrypts and decrypts data using a 56-bit key and 64-bit blocks. The proposed model provides a robust solution for data privacy preservation in IoT networks, which is crucial for protecting sensitive information from unauthorized access and data breaches. The proposed algorithm's performance analysis is evaluated using metrics, like computation time, memory, and fitness function. Results indicate that proposed ISOA based encryption model succeeded a greater performance, with a memory of 0.5170 MB, computational time of 1126.47 sec and fitness value of 1.3630.