memory address Research Articles (Page 8)

In the era of rapidly advancing technology, the limitations of conventional memory architectures have become a significant bottleneck in meeting the growing demands for data storage and processing. Emerging non-volatile memory technologies are increasingly closing the performance gap between traditional memory and storage solutions, driving innovations in memory cell design. This review provides an overview of conventional memory types, such as static random-access memory (SRAM), dynamic randomaccess memory (DRAM), and Flash memory, alongside emerging prototype memories like resistive randomaccess memory (RRAM), magnetoresistive randomaccess memory (MRAM), and phase-change memory (PCM). Emerging technology nowadays have a wide range of applications. Resistive random-access memory and spin torque transfer random access memory are the most promising memory for in-memory computing which is advanced beyond conventional von Neumann system, neuromorphic computing mimic human’s brain structure. Internet of things devices and wireless sensor devices make use of the low power consumption memory, and the security is provided by the stochasticity nature of randomaccess memory which is not desired and is considered as a challenge for memory cell.

The Fast Fourier Transform (FFT) method for solving the 1-D heat diffusion equation offers an efficient approach for resolving partial differential equations (PDEs) with various time steps . FFT is used to transform the 1-D heat diffusion equation into the frequency domain and back to the time domain through inverse FFT. Using mathematical modeling with initial and Dirichlet boundary conditions, the numerical solutions produced by FFT are compared with analytical solutions. The accuracy of the method is validated using MAE and MSE calculated in Matlab. At several time intervals , the obtained MAE and MSE values indicate a good agreement between the numerical and analytical solutions, with very small errors. Numerical stability analysis confirms the reliability of the FFT method across various The variation in time step has a significant impact on the accuracy and stability of the solution. Smaller time steps improve accuracy and stability but require longer computation times. The optimal time step selected in this study is Increasing the number of discretization points also enhances accuracy but implies an increase in computational load and memory usage. The FFT method demonstrates good numerical consistency with increasing

Simultaneous localization and mapping (SLAM), a pivotal technology in robotics, autonomous vehicles, and surveillance, has gained prominence with the emergence of edge intelligence. Developing energy-efficient, low-latency SLAM systems is essential due to resource constraints and real-time demands. Compute-in-memory (CIM) architectures have been proven to be efficient for matrix multiplications. However, applications for SLAM raise new challenges in memory access and computation aspects: the linear system solving (LS) requires row transformation and causes frequent CIM updates, while the backend optimization causes redundant memory access; back-end optimization dominates SLAM’s computation and requires high precision and high dynamic range. Thus, we propose SLAM-CIM, a visual SLAM backend processor for edge robotics. A dynamic-range-driven-skipping CIM macro is designed to realize energy-efficient floating point (FP)-multiply-and-accumulate (MAC) operations. A preconditional-conjugate-gradient-based in-memory linear solver (PILARS) is designed to achieve LS without additional row transformations. This reduces memory access by 2.08 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> and linear-system-solving latency by 3.84 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> . SLAM-CIM further minimizes CIM weight updates through incremental bundle adjustment (BA), increasing average CIM utilization by 2.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> . A silicon prototype is fabricated using 28-nm CMOS technology. The measurements show that SLAM-CIM achieves accurate and efficient SLAM operations with an average energy efficiency of 31.53 TFLOPS/W.

The computation-in nonvolatile memory (NVM-CiM) approach addresses the growing computational demands and the memory-wall problem faced by traditional processor-centric architectures. Computation-in-memory (CiM) capitalizes on the parallel nature of memory arrays enabling effective computation through multirow memristor reading and sensing. In this context, the conventional design of memory decoders needs to be accordingly modified for efficient multirow activation and parallel data processing. This article presents the design and optimization of address decoders for NVM-CiM system architectures, employing a cross-layer co-optimization approach that integrates circuit and architecture design with application requirements. Our methodology starts at the circuit level, examining various decoder designs, including cascaded, hierarchical, latched, and hybrid models. An in-depth application-level characterization follows, utilizing an extended NVM-CiM-capable gem5 simulator to assess the impact of these decoders on the mapping of CiM-friendly applications and the resulting system performance, particularly in facilitating rapid and efficient activation of multirow memory configurations. This holistic analysis allows us to identify the bottlenecks and requirements from the application side and adjust the design of the decoder accordingly. Our analysis reveals that Hybrid Decoders significantly decrease latency and power consumption compared to other decoder designs within NVM-CiM systems. This highlights the crucial role of the decoder’s row selection flexibility, reducing additional system-level data movement even at the expense of its performance, can substantially improve the overall efficiency of NVM-CiM systems.

Event-based cameras offer low latency and high-dynamic range imaging data in a sparse format that is well-suited for high-speed object tracking. Processing this sparse data in the same way as traditional camera data requires a great deal of unnecessary computation, making it difficult to take advantage of the high-effective frame rate for real-time processing. In this work, we propose an accelerator for high-speed object tracking on event-based camera data. SCIMITAR combines digital in-memory stochastic computing, in-situ stochastic stream generation, and multiple optimizations for utilizing input sparsity. SCIMITAR provides unparalleled performance with latency and energy that scale with sparsity. We demonstrate SCIMITAR performance on an object tracking application using circuit-level simulations of custom-designed compute-in-memory (CIM) macros and digital circuits. We achieve a frame processing rate of 26k frames/s with 100 regions-of-interest per frame and equivalent or better than state-of-the-art tracking accuracy. The accelerator achieves a peak throughput of 71 TOP/S and energy efficiency of 733 to 1702 TOP/S/W demonstrated on a range of event-based vision datasets, which is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5\times $ </tex-math></inline-formula> higher than other CIM solutions.

Prevalent large transformer models present significant computational challenges for resource-constrained devices at the Edge. While distributing the workload of deep learning models across multiple edge devices has been extensively studied, these works typically overlook the impact of failures of edge devices. Unpredictable failures, due to, e.g., connectivity issues or discharged batteries, can compromise the reliability of inference serving at the Edge. In this article, we introduce a novel methodology, called EASTER, designed to learn robust distribution strategies for transformer models against device failures that consider the tradeoff between robustness (i.e., maintaining model functionality against failures) and resource utilization (considering memory usage and computations). We evaluate EASTER with three representative transformers—ViT, GPT-2, and Vicuna—under device failures. Our results demonstrate EASTER’s efficiency in memory usage, and possible end-to-end latency improvement for inference across multiple edge devices while preserving model accuracy as much as possible under device failures.

The Internet of Things (IoT) has proliferated ubiquitous information exchange between the physical and cyber worlds through consumer electronics, with a focus on moving computing power to edge terminals. Computing-in-memory (CIM) technology has emerged as a competitive candidate for edge computing because of its low power consumption and high performance. In order to achieve accurate inference for neural network models, it is crucial to comprehend the source of errors in the CIM-based analog computing paradigm. In this work, we analyzed the impact of random noises and output stabling times on the Programmable Linear Random Access Memory (PLRAM)-based CIM chip. Experimental results show that the impact of random noise is negligible. The output stabling time can be treated as RC delay, which is related to the weight distribution. We proposed a weight reordering strategy to achieve better performance without sacrificing computation accuracy. Experiments with a commercial 11-keyword speech recognition model show a 74.4% runtime reduction while maintaining a 95.6% classification accuracy.

Precise identification of delamination defect based on optimized deep learning method to understand mechanical property reduction

Abstract Field effect transistors based on 2D layered material have gained significant potential in emerging technologies, such as neuromorphic computing and ultrafast memory response for artificial intelligence applications. This study proposes a facile approach to fabricate an optoelectronic artificial synapse for neuromorphic computing and light‐decoding information system by utilizing the 2D heterostructure of CrSBr/PtS2 to overcome circuit complexity. The CrSBr layer serves as a trapping layer, while PtS2, mounted on top of CrSBr, acts as a channel layer. PtS2 exhibits n‐type semiconductor behavior with a hysteresis that varies with the thickness of the underlying CrSBr layer. The heterostructure device, featuring a 96.3 nm thick CrSBr layer, exhibited a large memory window of 11.9 V when the gate voltage is swept from −10 V to +10 V. Various synaptic behaviors are effectively demonstrated, including paired‐pulse facilitation, excitatory postsynaptic current, optical spike number and intensity‐dependent plasticity using laser light at a wavelength of 365 nm. The device achieves 26 distinct output signals depending on the intensity of the incident laser light, ranging from 10 to 385 mW cm−2, enabling its applications for light‐decoded information security systems. Thus, the investigation presents a unique approach to artificial intelligence and cybersecurity systems.

Abstract Microprocessors, integrated data storage systems, and cache memories are just a few applications that can benefit from Static random access memory (SRAM). Computing In memory provides a solution for the von Neumann bottleneck problems. Simultaneously, it removes needless repeated data transmission between CPU and memory. Schmitt trigger was utilized for energy-efficient operation to get high reading and writing capacity. Two cross-coupled inverters with a transistor in between increase the design writing process. Furthermore, voltage boost logic is prioritized to maximize the node capacity. Using two dummy columns and dummy rows in RAM, the Replica technique controls the flow of signals via the core. The simulated results are compared to the designs that already exist. The simulation results show that the leakage power of the proposed design is 0.75 nw at 0.6 volts. The write static noise margin (WSNM) of the proposed cell is twice that of SEDF10T, which can be helpful for high-performance computing applications.

Transformer architectures have achieved state-of-the-art performance in various applications. However, deploying transformer models on resource-constrained platforms is still challenging due to its dynamic workloads, intensive computations, and substantial memory access. In this article, we propose a two-stage pipelined compute-in-memory (CIM) macro for effectively deploying and accelerating the feed-forward network (FFN) layers of transformer models. Two independent CIM arrays are designed to execute the two distinct linear projections in FFN layers, which are interconnected by co-designed analog rectified linear unit (ReLU) circuits to realize the nonlinear activation function. The analog multiply-and-add (MAC) results from the first CIM array are streamed directly to the analog ReLU circuits, and subsequently to the next CIM array for performing another linear projection. This architecture eliminates the need for analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) for internal results’ staging, thereby enhancing overall macro efficiency and reducing computing latency. A proof-of-concept macro is fabricated using TSMC 65-nm process and achieves 4.096 TOPS peak throughput, 4.39 TOPS/mm2 area efficiency, and 49.83 TOPS/W energy efficiency. To map transformer models onto the proposed macro, we quantize the FFN layers of BERTMINI model under per-token granularity for activations and per-tensor granularity for weights using quantization-aware training (QAT), which exhibits excellent accuracy across multiple benchmarks.

To explore cable interference in gas insulated substations (GIS), this paper proposes a reliable and efficient computational approach. The hybrid domain decomposition method-multilevel fast multipole algorithm (DDM-MLFMA) is presented herein. This technique determines the specifications of GIS cables for RG58 and AWG23. Self and mutual interference are identified utilizing very fast transient overvoltage (VFTO) transient interference signal.This hybrid technique offers a numerical simulation to replicate the impact of the VFTO interference signal. Utilizing the matrix-vector multiplication (MVX) product to address compression and approximation challenges, the hybrid approach proves reliable and pragmatic. Because of its computational nature and explicit factorization reduction, this strategy reduces computation time and memory requirements. Consequently, the system’s complexity follows a linear trend under this proposed approach. The computed results are juxtaposed with traditional methodologies to validate the effectiveness of the proposed algorithm.

A novel secure privacy-preserving data sharing model with deep-based key generation on the blockchain network in the cloud

Artificial intelligence (AI) has experienced substantial advancements recently, notably with the advent of large-scale language models (LLMs) employing mixture-of-experts (MoE) techniques, exhibiting human-like cognitive skills. As a promising hardware solution for edge MoE implementations, the computing-in-memory (CIM) architecture collocates memory and computing within a single device, significantly reducing the data movement and the associated energy consumption. However, due to diverse edge application scenarios and constraints, determining the optimal network structures for MoE, such as the expert’s location, quantity, and dimension on CIM systems remains elusive. To this end, we introduce a software-hardware co-designed neural architecture search (NAS) framework, CIM-based MoE NAS (CMN), focusing on identifying a high-performing MoE structure under specific hardware constraints. The results of the NYUD-v2 dataset segmentation on the RRAM (SRAM) CIM system reveal that CMN can discover optimized MoE configurations under energy, latency, and performance constraints, achieving 29.67× (43.10×) energy savings, 175.44×(109.89×) speedup, and 12.24× smaller model size compared to the baseline MoE-enabled Visual Transformer, respectively. This co-design opens up an avenue toward high-performance MoE deployments in edge CIM systems.

Memristors have emerged as promising devices for enabling efficient multiply-accumulate (MAC) operations in crossbar arrays, crucial for analog in-memory computing (AiMC). However, variations in memristors and associated circuits can affect the accuracy of analog computing. Typically, this is mitigated by on-chip training, which is challenging for memristors with limited endurance. We present a hardware-software codesign using magnetic tunnel junction (MTJ)-based AiMC off-chip calibration that achieves software accuracy without costly on-chip training. Hardware-wise, MTJ devices exhibit ultralow cycle-to-cycle variations, as experimentally evaluated over 1 million mass-produced devices. Software-wise, leveraging this, we propose an off-chip training method to adjust deep neural network parameters, achieving accurate AiMC inference. We validate this approach with MAC operations, showing improved transfer curve linearity and reduced errors. By emulating large-scale neural network models, our codesigned MTJ-based AiMC closely matches software baseline accuracy and outperforms existing off-chip training methods, highlighting MTJ's potential in AI tasks.

With the rapid advancement of 3D acquisition technologies, 3D sensors such as LiDARs, 3D scanners, and RGB-D cameras have become increasingly accessible and cost-effective. These sensors generate 3D point cloud data that require efficient algorithms for tasks such as 3D model classification and segmentation. While deep learning techniques have proven effective in these areas, existing models often rely on complex architectures, leading to high computational costs that are impractical for real-time applications like augmented reality and robotics. In this work, we propose the Multi-level Graph Convolutional Neural Network (MLGCN), an ultra-efficient model for 3D point cloud analysis. The MLGCN model utilizes shallow Graph Neural Network (GNN) blocks to extract features at various spatial locality levels, leveraging precomputed KNN graphs shared across GCN blocks. This approach significantly reduces computational overhead and memory usage, making the model well-suited for deployment on low-memory and low-CPU devices. Despite its efficiency, MLGCN achieves competitive performance in object classification and part segmentation tasks, demonstrating results comparable to state-of-the-art models while requiring up to a thousand times fewer floating-point operations and significantly less storage. The contributions of this paper include the introduction of a lightweight, multi-branch graph-based network for 3D shape analysis, the demonstration of the model's efficiency in both computation and storage, and a thorough theoretical and experimental evaluation of the model's performance. We also conduct ablation studies to assess the impact of different branches within the model, providing valuable insights into the role of specific components.

Stray light correction in hyperspectral imaging spectrometers has long been restricted by high computational requirements. This paper presents a low computational demand method, based on the matrix operations for spectrometer stray light correction, using an iterative approach to efficiently correct stray light across both spectral and spatial dimensions. The efficacy of this method is demonstrated through its application to simulated and real images, achieving an overall reduction of stray light by over 50%, with significantly reduced computation time and memory usage compared to the method by Zong et al. based on a sparse matrix [Appl. Opt. 45, 1111 (2006)10.1364/AO.45.001111APOPAI2155-3165]. By enabling stray light correction on general-purpose computers, this method enhances affordability and accessibility, promoting broader use and reducing measurement uncertainties in various hyperspectral imaging applications.

Finite automated system to design a high efficiency LLC resonant converter system for 3 kW. PV solar array

Abstract This paper develops a numerical procedure to accelerate the convergence of the Favre-averaged non-linear harmonic (FNLH) method. The scheme provides a unified mathematical framework for solving the sparse linear systems formed by the mean flow and the time-linearized harmonic flows of FNLH in an explicit or implicit fashion. The approach explores the similarity of the sparse linear systems of FNLH and leads to a memory-efficient procedure, so that its memory consumption does not depend on the number of harmonics to compute. The proposed method has been implemented in the industrial computational fluid dynamics solver Hydra. Three test cases are used to conduct a comparative study of explicit and implicit schemes in terms of convergence, computational efficiency, and memory consumption. Comparisons show that the implicit scheme yields better convergence than the explicit scheme and is also roughly 7–10 times more computationally efficient than the explicit scheme with four levels of multigrid. Furthermore, the implicit scheme consumes only approximately 50% of the memory required by the explicit scheme with four levels of multigrid. Compared with the full-annulus unsteady Reynolds-averaged Navier–Stokes simulations, the implicit scheme produces comparable results to URANS with computational time and memory consumption that are two orders of magnitude smaller.

Among several emerging architectures, computing in memory (CIM), which features <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">in-situ analog computation</b> , is a potential solution to the data movement bottleneck of the Von Neumann architecture for artificial intelligence (AI). Interestingly, more strengths of CIM significantly different from in-situ analog computation are not widely known yet. In this work, we point out that <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mutually stationary vectors (MSVs)</b> , which can be maximized by introducing <bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">associativity</b> to CIM, are another inherent power unique to CIM. By MSVs, CIM exhibits significant freedom to dynamically vectorize the stored data (e.g., weights) to perform agile computation using the dynamically formed vectors. We have designed and realized an SA-CIM silicon prototype and corresponding architecture and acceleration schemes in the TSMC 28 nm process. More specifically, the contributions of this paper are fivefold: 1) We identify MSVs as new features that can be exploited to improve the current performance and energy challenges of the CIM-based hardware. 2) We propose SA-CIM to enhance MSVs (input-reordering flexibility) for skipping the zeros, small values, and sparse vectors. 3) We propose channel swapping to enhance the zero-skipping technique. 4) We propose a transposed systolic dataflow to efficiently conduct conv3×3 while being capable of exploiting input-skipping schemes. 5) We propose a design flow to search for optimal aggressive skipping scheme setups while satisfying the accuracy loss constraint. The proposed ISSA architecture improves the throughput by 1.91× to 2.97× speedup and the energy efficiency by 2.5× to 4.2×.