memory address Research Articles (Page 9)

The principal purpose of this investigation is to present an approximate algorithm for solving third-kind Volterra integral equation with nonlinear vanishing delays using mesh-free techniques based on a radial basis function collocation scheme. This technique does not require background approximation cells, and the algorithm is efficient, has good stability and does not require much computer memory. A description of the approach for the proposed equations is provided. The error estimation of the proposed approach is also provided. The accuracy and reliability of the new scheme are demonstrated through numerical examples. Some of these examples have been compared with analytical solutions and moving least squares methods. The numerical results validate their agreement with theoretical error estimates.

Abstract The conventional reverse time migration utilizes regularly sampled computational grids to simulate wave propagation. Selecting the appropriate grid sampling is important for computational accuracy and efficiency. In general, the uniform-size grid cannot represent the complexity of the geology well. The grid may appear sparse in the low-velocity zone, especially in shallow depths where dispersion may occur. Conversely, it may appear excessively dense in the high-velocity zone, such as at greater depths or within a salt body, which results in higher computational memory and time consumption. To overcome these issues, we developed an efficient and accurate adaptive variable grid discretization method that automatically selects the vertical grid size based on the velocity, depth, and dominant frequency of the wavelet in elastic medium. Then we reformulated the elastic equations based on the adaptive variable grid by introducing a mapping relationship. To test the effectiveness, accuracy, and efficiency of the equation, we implemented it to both the forward propagation and migration of elastic wavefield. Synthetic numerical examples demonstrate that our proposed method can achieve elastic wavefield separation and no significant dispersion phenomenon. The multi-component imaging accuracy of reverse time migration is nearly equivalent to the traditional method, while significantly improving computational efficiency and saving storage space.

Ferroelectric materials, characterized by their high dielectric constants, piezoelectricity, and pyroelectricity, find numerous applications in electronic products such as computer memory, highly sensitive sensors, and sonar devices. Additionally, they hold potential applications in fields like solid-state refrigeration, with their performance often closely linked to their microstructural evolution, including phase transitions and domain switching. Phase-field methods serve as highly advantageous tools for exploring, revealing, and predicting mesoscale ferroelectric domain evolution. Within ferroelectric phase-field models, diverse types of domain structures of ferroelectric materials, such as bulk single crystals and thin films, can be simulated by setting different mechanical and electrical boundary conditions. Various types of ferroelectric phase transitions can also be studied by setting conditions in the models such as temperature variations and the application of external electric fields. Furthermore, by applying external electrical or mechanical stimuli in the phase-field models, behaviors such as ferroelectric domain switching can be observed. Here we first outline the fundamental framework of phase-field models, followed by a comprehensive overview of various phase transitions in ferroelectric materials, including ferroelectric-to-paraelectric and antiferroelectric-to-ferroelectric transitions. Additionally, the review summarizes how phase-field models facilitate the induction of ferroelectric domain switching through various experimental stimuli, including electric fields and mechanical fields. This review concludes by summarizing and prospecting potential new applications of the phase-field method in the study of ferroelectric phase transitions and domain switching.

Carbon nanotubes (CNTs) show promise for high energy efficiency electronic devices due to their high electrical conductivity. One possible application is in the fabrication of resistance-change computer memory, where the application of an external electrical bias can use a CNT layer as the switching element in a RAM cell. Memory cells of this type have been extensively demonstrated, where the electrical resistance of a switching layer of CNTs can be reversibly controlled by the application of external bias [1].To better understand these devices, we have developed a nanoscale model of their electrical switching. Towards this end, first-principles calculations of the electrical conductivity of CNT-CNT junctions were performed using the Density Functional Tight Binding (DFTB) in combination with the Non-Equilibrium Greens functions (NEGF) approach, enabling an improved understanding of the tunnelling of electrons across a range of CNT junctions [2]. These results demonstrate that the conductivity of CNT contacts depends on the overlap area between nanotubes and exponentially on the distances between the carbon atoms of the interacting CNTs. Secondly, we employed coarse-grained molecular dynamics [3,4] to produce nanoscale dense CNT film models like those used in the devices. We devise a set of metrics for characterising the structural properties of CNT films, and apply them to a set of model films designed to mimic those used in microelectronics devices. In order to understand how the geometrical properties of CNTs affect the film structure, we analyse films with different CNT chirality and length distributions. Unlike previous studies that focused on relatively low-density systems below ∼0.4 g/cm3, we also consider films with density of ∼0.6 g/cm3, as employed in experimentally fabricated CNT-based NRAM devices. By adding amorphous carbon to the film models, in varying amounts, we are then able to assess its effects. Finally, these two elements were combined to produce electrical simulations of the conductivity of the CNT films connected to TiN electrodes. These electrodes are shown to be partially oxidized during the device fabrication. The electrical conductivity in a device is characterized by formation of conduction paths formed by CNTs between the electrodes and connected via the CNT junctions. The conductivity is modulated by charging of CNTs and amorphous carbon present in the film.Using these simulations, we propose a resistance switching mechanism in TiN/CNT/TiN devices based on the physical movement of CNTs. During the initial operation of the device, oxygen is released from the oxidized bottom electrode and this readily reacts with individual CNTs to form charge trapping sites. Once these sites have become charged, they enable controllable movement of CNTs at the bottom electrode under the application of electric field. By reversibly connecting and disconnecting such CNTs from the bottom electrode, the electrical conductivity through the CNT film as a whole can be controlled.

Real-time computing and robust memory with deterministic chemical reaction networks

Tiny machine learning (TinyML) envisions executing a deep neural network (DNN)-based inference on an edge device for improving battery life, latency, security, and privacy. Toward this vision, recent microcontroller units (MCUs) integrate in-memory computing (IMC) hardware to leverage its high energy efficiency and throughput in vector–matrix multiplication (VMM). However, those existing works require large IMC hardware, severely increasing the area overhead. In addition, most existing works use analog–mixed-signal (AMS) IMC hardware, exhibiting limited robustness over process, voltage, and temperature (PVT) variations. Finally, none can support a practical software development framework such as TensorFlow Lite for Microcontrollers (TFLite-micro). Due to these limitations, those MCUs did not present the performance for the standard benchmark MLPerf-Tiny, which makes it difficult to evaluate them against the state-of-the-art neural (not necessarily IMC-based) MCUs. In this article, we design a new IMC-based MCU, titled iMCU, for TinyML to address those challenges. In the design process, we: 1) define the optimal set of acceleration targets and 2) devise an area-efficient computation flow that requires the least amount of IMC hardware yet still provides a significant acceleration. In addition, we develop: 1) state-of-the-art digital IMC macros and 2) create the accelerator based on the macros, which can support the proposed computation flow in a fully pipelined manner. Combining those innovations, we prototyped the iMCU in a 28-nm CMOS. The measurement results show that the iMCU significantly outperforms the prior IMC-based MCUs in compute density, energy efficiency, and SRAM density (total SRAM size/total SRAM area). It also achieves a compact footprint of 2.73 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^2$</tex-math> </inline-formula> .

Speeding up the communications on a cluster using MPI by means of Software Defined Networks

Some applications, such as satellites, require ultralow power and high-radiation resilience. We developed a12Tsoft error-resilient SRAM cell, TA-Quatro, to deliver in-memory computing (IMC) for those applications. Based on our TA-Quatro cell, we implemented an IMC circuit to support binary weights and ternary activations in a single SRAM cell. Our simulation under 28 nm FD-SOI technology demonstrates that the TA-Quatro IMC circuit maintains good IMC stability at a scaled supply of 0.7Vand achieves ternary activation without needing analog-to-digital converters. These advancements significantly enhance the power efficiency of the proposed IMC circuit compared to state-of-the-art works.

Assay for transposase-accessible chromatin with high-throughput sequencing (ATAC-seq) generates genome-wide chromatin accessibility profiles, providing valuable insights into epigenetic gene regulation at both pooled-cell and single-cell population levels. Comprehensive analysis of ATAC-seq data involves the use of various interdependent programs. Learning the correct sequence of steps needed to process the data can represent a major hurdle. Selecting appropriate parameters at each stage, including pre-analysis, core analysis, and advanced downstream analysis, is important to ensure accurate analysis and interpretation of ATAC-seq data. Additionally, obtaining and working within a limited computational environment presents a significant challenge to non-bioinformatic researchers. Therefore, we present Cloud ATAC, an open-source, cloud-based interactive framework with a scalable, flexible, and streamlined analysis framework based on the best practices approach for pooled-cell and single-cell ATAC-seq data. These frameworks use on-demand computational power and memory, scalability, and a secure and compliant environment provided by the Google Cloud. Additionally, we leverage Jupyter Notebook's interactive computing platform that combines live code, tutorials, narrative text, flashcards, quizzes, and custom visualizations to enhance learning and analysis. Further, leveraging GPU instances has significantly improved the run-time of the single-cell framework. The source codes and data are publicly available through NIH Cloud lab https://github.com/NIGMS/ATAC-Seq-and-Single-Cell-ATAC-Seq-Analysis. This manuscript describes the development of a resource module that is part of a learning platform named ``NIGMS Sandbox for Cloud-based Learning'' https://github.com/NIGMS/NIGMS-Sandbox. The overall genesis of the Sandbox is described in the editorial NIGMS Sandbox [1] at the beginning of this Supplement. This module delivers learning materials on the analysis of bulk and single-cell ATAC-seq data in an interactive format that uses appropriate cloud resources for data access and analyses.

The rapid advancements in artificial intelligence (AI) have demonstrated great success in various applications, such as cloud computing, deep learning, and neural networks, among others. However, the majority of these applications rely on fast computation and large storage, which poses significant challenges to the hardware platform. Thus, there is a growing interest in exploring new computation architectures to address these challenges. Compute-in-memory (CIM) has emerged as a promising solution to overcome the challenges posed by traditional computer architecture in terms of data transfer frequency and energy consumption. Non-volatile memory, such as Quantum-dot transistors, has been widely used in CIM to provide high-speed processing, low power consumption, and large storage capacity. Matrix-vector multiplication (MVM) or dot product operation is a primary computational kernel in neural networks. CIM offers an effective way to optimize the performance of the dot product operation by performing it through an intertwining of processing and memory elements. In this paper, we present a novel design and analysis of a Quantum-dot transistor (QDT) based CIM that offers efficient MVM or dot product operation by performing computations inside the memory array itself. Our proposed approach offers energy-efficient and high-speed data processing capabilities that are critical for implementing AI applications on resource-limited platforms such as portable devices.

In iterative Monte Carlo calculations for nuclear reactors, the inactive cycles should be calculated first to ensure that the source distribution is converged, and then the tallies of various parameters in the active cycles can begin. In order to acquire the mesh-free distribution of the fission source, this research proposes the functional expansion tallies (FET) source convergence diagnosis method in the Reactor Monte Carlo code, which is a self-developed stochastic simulation code maintained by the Reactor Engineering Analysis Laboratory of Tsinghua University. Due to the randomness in Monte Carlo calculations and the difficulty in determining the precise source convergence, this paper proposes a diagnostic tool based on function curve similarity and moving average, and proposes an online real-time source convergence diagnosis method. The FET online source convergence method can terminate the calculation of the inactive cycle in real time according to the convergence diagnostic tool; thus it can greatly decrease the calculation time. The precise and effective transfer of data between different meshes is a difficult issue of thermal and physical coupling. Converting two separate meshes and transferring the data are exceptionally difficult and complex tasks within the conventional nuclear thermal-physics coupling approach. By applying the FET method to nuclear thermal-physics coupling, the mesh-free continuous-space fission source distribution can be obtained, which is suitable for more complex meshes. Additionally, computational memory can be minimized by replacing (transforming) the data from numerous mesh power distribution data points with the coefficients of the function.

In-memory computing facilitates efficient parallel computing based on the programmable memristor crossbar array. Proficient hardware image processing can be implemented by utilizing the analog vector-matrix operation with multiple memory states of the nonvolatile memristor in the crossbar array. Among various materials, 2D materials are great candidates for a switching layer of nonvolatile memristors, demonstrating low-power operation and electrical tunability through their remarkable physical and electrical properties. However, the intrinsic device-to-device (D2D) variation of memristors within the crossbar array can degrade the accuracy and performance of in-memory computing. Here, we demonstrate hardware image processing using the fabricated 2D hexagonal boron nitride-based memristor to investigate the effects of D2D variation on the hardware convolution process. The image quality is evaluated by peak-signal-to-noise ratio, structural similarity index measure, and Pratt’s figure of merit and analyzed according to D2D variations. Then, we propose a novel two-step gradual reset programming scheme to enhance the conductance uniformity of multiple states of devices. This approach can enhance the D2D variation and demonstrate the improved quality of the image processing result. We believe that this result suggests the precise tuning method to realize high-performance in-memory computing.

With the advent of Big Data, traditional digital computing is struggling to cope with intricate tasks related to data classification or pattern recognition. To mitigate this limitation, software-based neural networks are implemented, but they are run in conventional computers whose operation principle (with separate memory and data-processing units) is highly inefficient compared to the human brain. Brain-inspired in-memory computing is achieved through a wide variety of methods, for example, artificial synapses, spiking neural networks, or reservoir computing. However, most of these methods use materials (e.g., memristor arrays, spintronics, phase change memories) operated with electric currents, resulting in significant Joule heating effect. Tuning magnetic properties by voltage-driven ion motion (i.e., magnetoionics) has recently emerged as an alternative energy-efficient approach to emulate functionalities of biological synapses: potentiation/depression, multilevel storage, or transitions from short-term to long-term plasticity. In this perspective, the use of magnetoionics in neuromorphic applications is critically reviewed, with emphasis on modulating synaptic weight through: 1) control of magnetization by voltage-induced ion retrieval/insertion; and 2) control of magnetic stripe domains and skyrmions in gated magnetic thin films adjacent to solid-state ionic supercapacitors. The potential prospects in this emerging research area together with a forward-looking discussion on future opportunities are provided.

The memory wall presents a significant challenge in computing, highlighting the increasing gap between processor and memory speeds. This discrepancy has sparked extensive research efforts to bridge the divide between memory units and processors. An approach is to minimize latency by integrating memory and processing units, specifically aiming to enhance memory processing capabilities. In this context, in-memory computing has emerged as a solution offering swift performance and streamlined data retrieval. This study addresses the memory wall issue by employing Block RAM (BRAM), a common component in digital design and FPGA programming, as an in-memory logic. The focus is on utilizing BRAM to store partial products from a Wallace Tree Multiplier (WTM), thereby facilitating rapid and efficient data storage within the FPGA fabric. The effectiveness of this method was demonstrated through simulation using Xilinx Vivado, showcasing its potential in overcoming the challenges posed by the memory wall.

The widespread use of maximum Jeffreys’-prior penalized likelihood in binomial-response generalized linear models, and in logistic regression, in particular, are supported by the results of Kosmidis and Firth (Biometrika 108:71–82, 2021. https://doi.org/10.1093/biomet/asaa052), who show that the resulting estimates are always finite-valued, even in cases where the maximum likelihood estimates are not, which is a practical issue regardless of the size of the data set. In logistic regression, the implied adjusted score equations are formally bias-reducing in asymptotic frameworks with a fixed number of parameters and appear to deliver a substantial reduction in the persistent bias of the maximum likelihood estimator in high-dimensional settings where the number of parameters grows asymptotically as a proportion of the number of observations. In this work, we develop and present two new variants of iteratively reweighted least squares for estimating generalized linear models with adjusted score equations for mean bias reduction and maximization of the likelihood penalized by a positive power of the Jeffreys-prior penalty, which eliminate the requirement of storing O(n) quantities in memory, and can operate with data sets that exceed computer memory or even hard drive capacity. We achieve that through incremental QR decompositions, which enable IWLS iterations to have access only to data chunks of predetermined size. Both procedures can also be readily adapted to fit generalized linear models when distinct parts of the data is stored across different sites and, due to privacy concerns, cannot be fully transferred across sites. We assess the procedures through a real-data application with millions of observations.

Background. The work is aimed at the development and research of rigorous methods for calculating multi-element emitting and re-emitting structures, consisting mainly of the same type of elements, as well as studying the physical processes occurring in them. An iterative approach to solving the internal problem is proposed, which allows minimizing the cost of computer time and computer memory. Aim. In this work, using the proposed approach, we solve the internal and external problems of electrodynamics for a symmetrical vibrator with a reflector made of parallel straight conductors. The convergence of the iterative process is studied, the currents on the elements of the structure, its input resistance and radiation characteristics are calculated. Methods. The research is based on a strict electrodynamic approach, within the framework of which, for the specified structure in the thin-wire approximation, an integral representation of the electromagnetic field is formed, which, when considered on the surface of conductors together with boundary conditions, is reduced to a system of Fredholm integral equations of the second kind, written relative to unknown current distributions on conductors (internal task). The solution of the internal problem within the framework of the method of moments is reduced to solving a SLAE with a block matrix. Results. A mathematical model of a radiating structure is proposed, which is a symmetrical vibrator with a reflector made of parallel straight conductors. The internal and external problems of electrodynamics are formulated and solved for given parameter values. An effective algorithm for calculating the block matrix of SLAEs is proposed. Recommendations are given for the selection of systems of projection functions within the framework of the method of moments. The convergence of the iterative process for solving an internal problem of electrodynamics has been studied. The input resistance of the structure and the basic characteristics of its radiation are determined. Conclusion. A rational choice of systems of projection functions, based on the properties of the structure and its constituent elements, makes it possible to significantly reduce the size of the SLAE matrix and, accordingly, reduce computational costs. Taking into account the properties of the structure and its constituent elements also makes it possible to construct effective algorithms for calculating the SLAE matrix. It is shown that the convergence of the iterative process may be absent near resonant frequencies, therefore, when solving the internal problem, a combined approach should be used, which involves the use of both rigorous and approximate methods for solving SLAEs. At non-resonant frequencies, the iterative approach demonstrates its effectiveness. It is concluded that for such structures it is advisable to distinguish between resonant and non-resonant operating modes. In the non-resonant mode, the current functions have a fairly smooth dependence on frequency; in the resonant mode, these dependences become quite sharp and difficult to predict. In this regard, the task of developing an iterative approach to solving the internal problem of electrodynamics in resonant operating modes seems relevant.

Advanced electronic semiconducting Van der Waals heterostructures (HSs) are promising candidates for exploring next-generation nanoelectronics owing to their exceptional electronic properties, which present the possibility of extending their functionalities to diverse potential applications. In this study, GeTe/MoTe2 HS are explored for nonvolatile memory and neuromorphic-computing applications. Sputter-deposited Ag/GeTe/MoTe2/Pt HS cross-point devices are fabricated, and they demonstrate memristor behavior at ultralow switching voltages (VSET: 0.15V and VRESET: -0.14V) with very low energy consumption (≈30 nJ), high memory window, long retention time (104 s), and excellent endurance (105 cycles). Resistive switching is achieved by adjusting the interface between the Ag top electrode and the heterojunction switching layer. Cross-sectional transmission electron microscope images and conductive atomic force microscopy analysis confirm the presence of a conducting filament in the heterojunction switching layer. Further, emulating various synaptic functions of a biological synapse reveals that GeTe/MoTe2 HS can be utilized for energy-efficient neuromorphic-computing applications. A multilayer perceptron is implemented using the synaptic weights of the Ag/GeTe/MoTe2/Pt HS device, revealing high pattern accuracy (81.3%). These results indicate that HS devices can be considered a potential solution for high-density memory and artificial intelligence applications.

H-SLAM: Hybrid direct–indirect visual SLAM

Despite its promising potential for Artificial Intelligence (AI) applications, current In-Memory Computing (IMC) technology faces a variety of challenges before mass production. One of the major challenges we face is the absence of efficient toolchains for deploying canonical networks on IMC chips. To address this issue, we propose a co-designed framework that integrates circuit, toolchain, and system elements specifically for IMC. More specifically, our framework consists of several key techniques to improve the key performance including (a) an 8-bit hardware-friendly Quantization-Aware Training (QAT) approach to quantify the deep learning network from floating-point data to fixed-point data, (b) a novel operator optimization technique to increase the computing precision when running the algorithm models on the IMC chips, and (c) an efficient mapping strategy based on the Integer Linear Programming (ILP) approach to improve the computation resource utilization of the IMC array. We assess our method on our 40nm eFlash-based IMC SoC chip with voice recognition, speech noise reduction, and person detection tasks. Our experimental results show an accuracy over 94.60% in a quiet environment and 87.27% in a white noise environment and a false recognition rate below 1 time per 24 hours for voice recognition, a 21.53% improvement for the Perceptual Evaluation of Speech Quality (PESQ) for noise reduction, and a 97.80% accuracy in person detection.

Human pose estimation (HPE) is a promising solution for accurately understanding the state and context of human actions in virtual reality (VR). A high frame rate with low-power HPE processing is required for a realistic user interaction experience in battery-limited mobile devices. The proposed HPE accelerator is a computing-in-memory (CIM) based accelerator that computes depth-wise separable convolution (DWSC) of a lightweight HPE network. Three key features contribute to a resource-efficient CIM accelerator: 1) Dual-mode CIM computes DWSC with a reconfigurable homogenous architecture, resulting in 2.68 times higher throughput than previous analog CIMs. 2) Effective layeraware unrolling performs bit-parallel computation on dualmode CIM with fewer ADC operations, achieving 46 times higher throughput than before. 3) Adaptive fused inter-macro balancing improves latency balance in layer fusion execution, leading to a 57.0 % higher frame rate than before. The proposed HPE accelerator is implemented in 28nm CMOS technology. It achieves higher computation resource utilization and operates HPE with a low energy-delay product of 27.6 uJ7s in mobile VR devices.