GaN power transistors have emerged as a promising solution for high-power (>1kV) and high-frequency (>100 kHz) applications due to GaN’s material properties, including wide bandgap (3.4eV), high critical electric field (3.3 MV/cm) and an electron saturation rate which is 2.8 times that of silicon [1]. Both vertical and lateral power transistor configurations require a MIS gate structure, which includes the deposition of a dielectric layer, most often Al2O3. However, the performance of these devices is significantly influenced by the quality of the dielectric/GaN interface and the choice of gate dielectric [2].For this reason, surface preparation is critical to minimize interface trap density by reducing defects and impurities prior to dielectric deposition, and thus enhancing electrical performance and stability. The search for an effective surface treatment method, whether wet or dry, has been the focus of several studies [3]. However, many factors were not taken into consideration, such as the re-oxidation of GaN prior to dielectric deposition, the dependence of interface quality on the nature of the dielectric and its thickness, hence the need for an in-situ approach that treats interface and dielectric quality in a non-separate way.In this study, we first focus on in-situ atomic layer cleaning of the GaN surface using different plasma atmospheres (NH3, Ar, H2, N2) to investigate their impact on the interface under the same conditions with a reference dielectric Al2O3. Secondly, we explore the integration of an ALD-ternary high-K dielectric, AlSiO, through two approaches, both conducted without an air break to preserve the benefits of plasma cleaning. The approaches are either multilayer mode (Al2O3/SiO2) or mixed mode.To assess interface quality and dielectric performance, MOS capacitors (MOSCAPs) are fabricated. Their characterization is conducted through capacitance-voltage (C-V) and current-voltage (I-V) measurements, complemented by hard X-ray photoelectron spectroscopy (HAXPES).Our goal is to achieve a lower hysteresis (ΔVFB) < 50 mV and a flat band voltage (VFB) shifting towards 0V for the Al2O3/GaN interface and positive values for the AlSiO/GaN interface. Our results demonstrate significant improvements in ΔVFB. Among the different plasma cleaning atmospheres tested, NH3/N2 plasma treatment at low power was selected as the optimal choice, offering a balance between minimizing ΔVFB and achieving a VFB close to 0V.This was followed by the deposition of AlSiO with a low-silicon matrix, the comparison between the effectiveness of both approaches (Mixed and multilayer) is still ongoing .These process conditions will be further used for 200mm vertical power transistors to investigate their impact on device performance.[1] Catherine Langpoklakpam et al., « Vertical GaN MOSFET Power Devices », Micromachines 14, no 10 (octobre 2023): 1937, https://doi.org/10.3390/mi14101937.[2] Anthony Calzolaro, Thomas Mikolajick, et Andre Wachowiak, « Status of Aluminum Oxide Gate Dielectric Technology for Insulated-Gate GaN-Based Devices », Materials 15, no 3 (janvier 2022): 791, https://doi.org/10.3390/ma15030791.[3] Yutao Cai et al., « Effect of Surface Treatment on Electrical Properties of GaN Metal–Insulator–Semiconductor Devices with Al2O3 Gate Dielectric », Japanese Journal of Applied Physics 59, no 4 (mars 2020): 041001, https://doi.org/10.35848/1347-4065/ab7863.
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