STMicroelectronics (France)

Abstract In this paper, we present an experimental study of a new method based on Hot Hole Injection (HHI) for the embedded Select in Trench Memory (eSTM™) cell. An in-depth investigation of the floating implant provides insight into the erase mechanism. Electrical characterizations across the wafer reveal two distinct cell behaviors. The objective is therefore to identify the origin of these behaviors. It is demonstrated that no wafer-level effect is involved. Instead, this variability comes from process fluctuation of the Adjust threshold voltage (AdV T ) dose and the Lightly Doped Drain (LDD) depth. To optimize this new erase operation, a set of electrical characterizations are carried out on various process splits of the device. This enables the identification of a better trade-off that increases the cell’s erase probability. However, the optimized device has erasure failures. Future work should aim to achieve completely reliable operation (i.e. 100% of the expected behavior) while reducing the current consumption of the cells.

We report a <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$54 \times 42$</tex>-resolution SPAD-based LIDAR receiver SoC leveraging 3D-stacked <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$65 / 40 ~\text{nm}$</tex> technology with high-frequency TDC and 2 counters for ToF and intensity exposure, with peripheral memories used for image signal processing (ISP) frame stores, point cloud generation & HDR management. A hybrid on-chip & package-embedded 25V boost converter is described integrating SPAD supply generation synchronized with sensor frame timing. The sensor is integrated in a LIDAR module for 9.6m ranging with <1cm error.

As modern Integrated Circuits (ICs) incorporate increasingly smaller transistors, the occurrence of manufacturing defects within standard cells (intra-cell defects) has risen. Detecting and localizing these defects is essential for ensuring a rapid yield ramp-up and maintaining a low-test escape rate. To address intra-cell defects, Cell-Aware (CA) methodology was introduced, but it relies on time-consuming analog SPICE simulations for standard cell characterization. This paper introduces Transistor Undetectable Defect Eliminator (TrUnDeL), a graph-based methodology designed to expedite the CA model generation process. TrUnDeL identifies undetectable defects for each stimulus applied to cell inputs, excluding them from required analog simulations. TrUnDeL was tested on two FD-SOI standard cell libraries (P28 and C28) from STMicroelectronics. The results show that, for combinational cells, the CA model generation process time was reduced by a factor of three compared to standard analog-based methods without compromising accuracy. To efficiently address sequential cells, modifications to the classical TrUnDeL flow were implemented, resulting in a 30% reduction in CA model generation time for sequential cells, again without compromising accuracy. TrUnDeL was also tested on a 4x4 SRAM case study, maintaining accuracy across all memory modules. Finally, the paper introduces Layout-TrUnDeL for addressing layout defects, proving effective on 8 test-case cells without misclassification.

The integration of PN diodes on bulk silicon technologies often leads to shot noise and significant parasitic effects such as latch-up which arises when a parasitic transistor is unintentionally triggered, leading to undesired current flows. To address these issues, and enable operation in higher voltage ranges, this work investigates the use of unexplored polysilicon PIN diodes implemented on an insulating area as an alternative solution to PN diodes integrated on bulk substrates. The geometric design and process optimizations of the PIN diode structure are explored to optimize its performances (forward and leakage currents, series resistance, threshold, and breakdown voltages) while ensuring compatibility with low-cost analog circuits fabricated in an 40nm technology dedicated to IoT applications. Compared to classical PN diodes, PIN diodes require a simple fabrication process and can provide a breakdown voltage twice higher. However, this improvement comes at the expense of an increased leakage current and series resistance.

Photonic integrated devices are progressively evolving beyond passive components into fully programmable systems, notably driven by the progress in chalcogenide phase-change materials (PCMs) for non-volatile reconfigurable nanophotonics. However, the stochastic nature of their crystal grain formation results in strong spatial and temporal crystalline inhomogeneities. Here, the concept of spatially-controlled planar guided crystallization is proposed, a novel method for programming the growth of optically homogeneous low-loss Sb2S3 PCM, leveraging the seeded directional and progressive crystallization within confined channels. This guided crystallization method is experimentally shown to circumvent the current limitations of conventional PCM-based nanophotonic devices, including a multilevel non-volatile optical phase-shifter exploiting a silicon nitride-based Mach-Zehnder interferometer, and a programmable metasurface with spectrally reconfigurable bound state in the continuum. Precisely controlling the growth of PCMs to ensure optically uniform crystalline properties across devices is the cornerstone for the industrial development of non-volatile reconfigurable photonic integratedcircuits.

The exchange interaction has been successfully used to mediate qubit entanglement in various semiconductor quantum devices. Using the finite-element method, we combine a nonlinear Poisson solver with single-and many-body Schrödinger solvers to simulate the exchange interaction between a pair of spin qubits in a fully depleted silicon-on-insulator (FD-SOI) device. We also modify the Poisson solver to account for charge impurities and evaluate the effect of a single impurity on the exchange interaction strength, including its dependence on the impurity's position. The effect of the impurity on the exchange strength is then analyzed to calculate the average two-qubit gate fidelity achievable via the exchange interaction when the system is subject to charge noise arising from a charge randomly tunneling in and out of an interface impurity trap. The presented approach demonstrates the possibility of simulating key quantum-device performance metrics, such as two-qubit gate fidelity, starting only from the device geometry.

This paper presents J3DAI, a tiny deep neural network-based hardware accelerator for a 3-layer 3D-stacked CMOS image sensor featuring an artificial intelligence (AI) chip integrating a Deep Neural Network (DNN)-based accelerator. The DNN accelerator is designed to efficiently perform neural network tasks such as image classification and segmentation. This paper focuses on the digital system of J3DAI, highlighting its Performance-Power-Area (PPA) characteristics and showcasing advanced edge AI capabilities on a CMOS image sensor.To support hardware, we utilized the Aidge comprehensive software framework, which enables the programming of both the host processor and the DNN accelerator. Aidge supports post-training quantization, significantly reducing memory footprint and computational complexity, making it crucial for deploying models on resource-constrained hardware like J3DAI.Our experimental results demonstrate the versatility and efficiency of this innovative design in the field of edge AI, showcasing its potential to handle both simple and computationally intensive tasks.

A fully integrated wideband THz autodyne frequency-modulated continuous-wave (FMCW) radar is reported in this work. The core of the transmitter is a five-stage voltage-controlled ring oscillator (VCRO). Wideband operation is achieved through the radiation of the fifth harmonic (<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5{f}_{o}$ </tex-math></inline-formula>) of the proposed VCRO. Additionally, an on-chip folded slot antenna is designed for radiation and reception of voltage-controlled oscillator (VCO)’s signal while providing the optimum matching condition at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$5{f}_{o}$ </tex-math></inline-formula>. The radar is fabricated in a 55-nm BiCMOS process using only CMOS transistors with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${f}_{T}/{f}_{\max }=255$ </tex-math></inline-formula>/290 GHz. The radar achieves a peak equivalent-isotropically radiated power (EIRP) of 6.2 dBm using a hyper-hemispherical silicon lens and a 57 GHz bandwidth with an in-band power variation of 5.8 dB. It consumes 152 mW of dc power and occupies an area of 0.16 mm2. The autodyne radar topology utilizes the oscillator transistors as the mixing element, generating an intermediate frequency (IF) signal that is extracted from the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm { DD}}$ </tex-math></inline-formula> line. Simulation results of the autodyne operation and IF generation mechanism are provided, verifying the dual operation of VCO as a transmitter and receiver. At last, the radar is tested in a focal imaging setup to take images of human teeth and capture the cavities and root canals inside the teeth. To the best of our knowledge, this radar achieves the highest bandwidth and smallest area among the VCO-based CMOS radars in the 100–500 GHz range.