A 22Gb/s-54Gb/s Reconfigurable PAM-2/4/8 DSP-based Transmitter with 14-tap Feedforward Equalization

Skin effect and dielectric loss in super-long cable will cause nonlinear attenuation at different signal frequency, and in addition, coupling noise and thermal noise also cause signal distortion at the receiver end. These factors seriously affect the signal transmission speed in the super-long cable. Especially, in the field of exploration of shale gas and bed methane, the transmission cable is also used to transport high-precision synchronization pulse signal, and the synchronization pulse must reach the microsecond accuracy, which is used for data phase calibration. A synchronization signal is a high frequency signal, which suffers more severe attenuation and noise interference. At the receiving end, the sync pulse signal will be drowned in the noise environment, and so it is difficult to restore the original signal.#br#Although fiber can achieve a high transfer rate, but the fiber cable cannot transmit power energy; in addition, the tensile strength and heat resistance of the fiber are much worse than copper cable, these weaknesses limit its application in such industry. Therefore, an effective balancing algorithm is necessary to overcome the propagation effects and interference in a super-long copper cable. However, conventional equalization techniques have well-balanced effect for the short-range communications, but for the long-distance communication, they often have poorly balanced results. In order to solve the above problem and improve the long cable signal transmission speed, this paper presents a new balanced portfolio structure; the new structure uses feed-forward equalizer (FFE) as the pre-stage, and decision-feedback equalizer (DFE) as the post stage to form a new structure. The combination structures can effectively utilize the flexibility of FFE and overcome the problem of error diffusion in DFE. By mathematical modeling and simulation, this paper gives the best combination factors. Furthermore, based on the improved structure, a new convergence algorithm is proposed, which uses the arc tangent function combined with three error converge factors to form a converging function, and it has the advantages of fast convergence and steady-state error. Simulation results show that the FFE-DFE combination equalizer has low computational complexity, fast convergence, and strong channel tracking capability; in addition, it can speed up the data processing speed, and better respond to the real variation of the channel. Simulation results show also that the performance is improved by 50% by eliminating inter-symbol interference and noise.#br#The real circuit board based on the new algorithm have been tested in the East China Petroleum Bureau, the test results show that the algorithm can rectify 160 dB signal distortion, and the transmission speed can reach 5 Mbps in 6 dB signal to noise ratio.

Conventional current-mode summation utilized in feed-forward equalization (FFE) has disadvantages in power consumption and linearity and thus becomes less attractive when high-speed low-power equalization is required. A Multi-Capacitor (MultiCap) structure is presented to overcome these disadvantages by supporting voltage-mode summation. This passive structure replaces the current-summation block of the transmit FFE and has zero power consumption. A set of equations are derived to estimate the useable value of the MultiCap, of which the range is bounded by I/O pitch, receiver sensitivity, and other parameters. The parasitics of this device are proven to be negligible. Simulation in 0.13µm standard CMOS process shows that the MultiCap structure could enable a power saving of more than 90% over the conventional current-mode FFE.

In this paper, we propose a joint feedforward equalizer (FFE) and an error-based feedforward equalizer (Err-FFE) to eliminate the serious inter-symbol interference and high-frequency colored noise for 100 Gb/s 4-level pulse-amplitude modulation (PAM4) optical systems. The proposed Err-FFE is first designed to replace the joint post-filter (PF) and maximum likelihood sequence estimation (MLSE). The Err-FFE algorithm has only 15% computational complexity compared to the joint PF and MLSE. Moreover, experimental results show that the performance of joint FFE and Err-FFE algorithm is much better than that conventional FFE, and is comparable with that of FFE joint with PF and MLSE. In conclusion, the proposed Err-FFE has both low computational complexity and excellent performance for PAM4-based optical systems, which indicates its potential for applications in low-cost and low-power short-reach optical interconnects.

An equalizer architecture based on asynchronous sampling is described. The circuit implementation is a hybrid feed-forward equalizer (FFE) using three digital postcursor taps realized via level-crossing samplers (LCSs) and inverter-based delays. Utilizing a current mode logic (CML)-based summer stage, an analog main tap and digital postcursor taps are combined into an inductively tuned resistor load. With a 0.67-mV-rms simulated output-referred noise, the FFE has better noise performance than a conventional continuous-time linear equalizer (CTLE) and a slicer/latch-based decision feedback equalizer (DFE) circuit. Moreover, it exhibits very good linearity and group delay performance suitable for an equalizer. Using inverter-based delays enables area efficiency as well as the capability to tune the delay across process voltage and temperature (PVT) variations. Since the FFE is an event-driven combinational logic based on the incoming data, it does not require synchronous sampling coming from a high-speed clock and data recovery (CDR), and it is advantageous for high-speed and multirate operation as its power consumption scales with the data rate. Fabricated in 40-nm CMOS technology, the hybrid FFE achieves energy per bit of 2.7 pJ/bit with a 20-dB Nyquist insertion loss link at the 28.57-Gb/s nonreturn to zero (NRZ) data rate.

Electromagnetic interference (EMI) signals, which radiate in the environment and cause the malfunction of electronic devices in proximity, are generated due to the common mode (CM) noise in differential circuits. This CM noise is produced because of the imbalance in the charging and discharging paths of the driver and equalizer circuits in the transmitter. However, the effects of the equalizer on CM noise have not been examined. This paper systematically investigates the effect of different feed forward equalizer (FFE) configurations on EMI-related CM noise in a 56-Gbps four-level pulse-amplitude modulation (PAM-4) optical transmitter, aiming to provide an optimized configuration with low CM noise and power consumption, while providing high compensation. The simulation results show that an asymmetric equalizer significantly improves the compensation performance. However, the offset in differential pair of output stage should be minimized to decrease the CM noise generated from the FFE.

We illustrate a new type of nonlinear obtained by placing a decision feedback and a decision feedforward in parallel. This type of called a parallel decision feedback and feedforward equalizer or, briefly, a equalizer, is characterized by substantially reduced error propagation if the eye diagram is open at the input of the decision device of the decision feedback and of the first decision device of the decision feedforward equalizer. The composite may be conveniently built up using a single decision device in the decision feedforward equalizer.

To solve the high bit error rate (BER) problem of conventional 56-Gb/s nonreturn-to-zero (NRZ) transceivers under high-insertion loss (IL) channels, this study proposes a high-speed adaptive duobinary (DB) digital detector based on the feed-forward equalizer (FFE) and the maximum likelihood sequence detector (MLSD). In this detector, adaptive FFE is combined with channel characteristics to generate DB signals and complete equalization, thus extending the transmission bandwidth and eye height and allowing a larger sampling phase offset. The parallel MLSD is used to complete the detection and decoding of DB signals to reduce the BER. An adaptive algorithm is proposed to avoid the long convergence time of the conventional zero-forcing (ZF) algorithm applied to the DB detector, so that it can be applied to various bit rates and IL channels. In this study, the verification of this DB detector is accomplished at 56 Gb/s. The platform based on a 56-Gb/s analog front-end chip (AFEC) and field-programmable gate array (FPGA) proves that the detector can work well in 12–56 Gb/s and multiple IL channels. The BER was less than 2e-8 at 56 Gb/s on −42-dB channel loss at 28 GHz. The structure can be well used for higher rate transceivers, such as 112 Gb/s.

Inclusive and intensive performance analysis of electrical equalizers in a short-reach optical system using four-level pulse amplitude modulation (PAM-4) is presented in this paper. Two equalizers are used—a feedforward equalizer and decision feedback equalizer using the least mean square algorithm. The sensitivity to cut-off frequency for the transmitter and receiver filters, fiber length and number of equalizers taps in the means of the bit error rate vs. optical input power are shown. The analysis reveals the considerable impact of the filters’ bandwidth, particularly in the receiver, on the equalizer performance. These results and their reasons are analyzed and broadly discussed.

A 10 Gb/s NRZ receiver with feedforward equalizer and CDR is described. The CDR incorporates an LC oscillator with a range of 8.3 to 11.1 GHz and a new glitch-free binary PFD. The glitch-free architecture minimizes the jitter generation of the CDR and increases jitter tolerance. The CDR loop employs a V/I converter with two independent charge-pumps for FD and PD signals to achieve fast acquisition and low jitter generation simultaneously.

The increasing demand for higher network data rates by new businesses and entertainment has never been fulfilled. Mixed-signal PAM - 4 transceivers prevail over their ADC - DSP counterparts in energy efficiency and chip area, but they have difficulties operating over high - loss links. Typically, a continuous-time linear equalizer (CTLE) and a multi-tap decision-feedback equalizer (DFE) are implemented in a mixed-signal receiver (RX). However, when the data rate reaches 112Gb/s, the implementation of the DFE suffers from stringent feedback timing. Direct DFE works only at 100Gb/s in an optical receiver [1], leaving no room for feedforward error correction (FEC). A speculative 1 - tap DFE is implemented in [2], but it requires an 8-tap feedforward equalizer (FFE) at the transmitter (TX) to generate a 1+0.5D response; this may be impractical without knowing the characteristics of the entire channel. Another drawback of a speculative DFE is the large 1 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">st</sup> -tap latency, which brings about challenges in realizing two or more taps. In addition, the DFE does not compensate for pre-cursor inter-symbol interference (ISI), which becomes significant for channels with higher loss. Without a DFE, the CTLE only covers a small loss of up to 10dB [3,4]. This paper presents a 112Gb/s mixed-signal transceiver using an RX analog FFE with adaptive pre- and post-cursor ISI equalization in 28nm CMOS, compensating for 20.8dB loss at a power efficiency of 2.29pJ/b.

We experimentally studied the polarization mode dispersion (PMD) tolerance of an feed-forward equalizer (FFE) electronic dispersion compensation (EDC) IC in the absence of adaptive control, in 43-Gbit/s RZ-DQPSK transmission. Using a 3-tap FFE IC composed of InP HBTs, differential group delay (DGD) tolerance at a 2-dB Q penalty is shown to be extended from 25ps to up to 29ps. When a polarization scrambler is used, the tolerance is further extended to 31ps. This value is close to the tolerance obtained with adaptive control, without a polarization scrambler.

Introduction Indoor infrared wireless systems using diuse channels are considered as the best form in respect of the network exibility. Infrared wireless system using ono keying code-division multiple-access (OOK-CDMA) has been proposed to realize multiple access in indoor infrared wireless communications, and the performance is analyzed on diuse channels [1]. It is shown in [1] that the bit error rate (BER) of indoor infrared wireless systems using OOK-CDMA on diuse channels is degraded excessively owing to the eects of ISI. To mitigate the eects of ISI, some equalization schemes for infrared wireless systems have been discussed [2]-[5]. The performance of the OOK-CDMA with the decision-feedback equalizer (DFE) and that of the OOK-CDMA with the decision-feedforward-andfeedback equalizer (DFFE) have been evaluated, and it is shown that the system with the DFFE has better performance than that of the system with the DFE [4]. The performance of the DS-CDMA with the feedfo

As four‐level pulse‐amplitude‐modulation (PAM‐4) signal becomes widely adopted for high‐speed wireline communication, robust equalization is crucial due to reduced eye‐opening and increased sensitivity to channel loss, compared to PAM‐2. Utilizing analog‐to‐digital converters and digital signal processing with a feed‐forward equalizer (FFE) and a decision‐feedback equalizer (DFE), conventional equalizer adaptation may result in suboptimal bit‐error‐rate (BER) performance. This letter introduces an improved training algorithm to obtain the optimal equalizer configuration (i.e., main tap position in FFE and the DFE tap coefficient). The experimental results demonstrate superior BER performance of the proposed algorithm compared to the conventional approaches.

This paper presents the experimental characterization of a High-Speed Serial Interface (HSSI) for automotive microcontroller applications designed in 28 nm planar CMOS technology, verified over automotive corners and operating up to 11 Gb/s. The impedance of the full-rate voltage-mode transmitter can be tuned by activating several driver replicas. It also features an 8-tap Feed-Forward Equalizer (FFE) with taps programmable in steps of 1/16. The analog front-end of the receiver cascades a Variable-Gain Amplifier (VGA) and a Continuous-Time Linear Equalizer (CTLE), which can be individually tuned. The receiver is based on a half-rate architecture and features a 3-tap Decision-Feedback Equalizer (DFE), one tap being speculative to relax timing constraints; another VGA is embedded in the DFE summing node. The subsequent data and edge samplers are offset-compensated. The circuit is experimentally characterized over automotive corners at 6.25 Gb/s and 11 Gb/s on highly-reflecting PCB channels with up to 14.5 dB loss, demonstrating operations at bit-error ratio (BER) below 10−12 up to 11 Gb/s. The HSSI occupies an area of 0.08 mm2 and consumes 8.4 mW/Gb/s at 11 Gb/s and 6.2mW/Gb/s at 6.25 Gb/s.

We present an adaptation scheme for a wireline-receiver equalizer composed of a feed-forward equalizer (FFE) and a decision-feedback equalizer (DFE), where the FFE is a cascaded connection of a high-frequency equalizer (HFEQ) and a low-frequency equalizer (LFEQ). The HFEQ is adjusted by using the conventional filter-pattern method. For the LFEQ adjustment, we used a modified filter-pattern method where the pattern matching is performed based on the mark ratio (i.e., the probability of `1'), to enhance the gain of the parameter-adjusting feedback loop. The adaptation is performed in the background, i.e., while data is being received.