A modular partitioning approach for asynchronous circuit synthesis

In the VLSI circuits, power dissipation is a critical design parameter and it plays a vital role in the performance of different digital systems. The decrease in chip size along with the increase in chip density and complexity will increase the difficulty in designing higher performance and low power digital systems. Therefore, achieving a fast and low power system is the major concern of VLSI designers. Most of the digital systems have different math operations in their architectures. This paper focuses on the multiplication operation. Multiplication requires more iterations, long time, large area, and consumes high power of the digital system compared with the other basic computation operations. Hence to improve the system's performance, it is required to design a high speed and low power multiplier. In this paper, a dynamic power dissipation is targeted; therefore, different designs of multiplier algorithms such as a sequential multiplier, array multiplier, Booth’s multiplier (Radix-2), and modified Booth’s multiplier (Radix-4) are proposed to investigate the design that consumes the lowest dynamic power. New techniques such as VHDL and Basic Logic Elements are presented and applied to the proposed designs. The VHDL approach satisfies the highest optimization criteria in dynamic power at 87% for the sequential multiplier than the traditional ones.

Project Final Report for "100kW Energy Transfer Multiplexer Power Converter Prototype Development Project" prepared under DOE grant number DE-FG36-03GO13138. This project relates to the further development and prototype construction/evaluation for the Energy Transfer Multiplexer (ETM) power converter topology concept. The ETM uses a series resonant link to transfer energy from any phase of a multiphase input to any phase of a multiphase output, converting any input voltage and frequency to any output voltage and frequency. The basic form of the ETM converter consists of an eight (8)-switch matrix (six phase power switches and two ground power switches) and a series L-C resonant circuit. Electronic control of the switches allows energy to be transferred in the proper amount from any phase to any other phase. Depending upon the final circuit application, the switches may be either SCRs or IGBTs. The inherent characteristics of the ETM converter include the following: Power processing in either direction (bidirectional); Large voltage gain without the need of low frequency magnetics; High efficiency independent of output load and frequency; Wide bandwidth with fast transient response and; Operation as a current source. The ETM is able to synthesize true sinusoidal waveforms with low harmonic distortions. For a low power PM wind generation system, the ETM has the following characteristics and advantages: It provides voltage gain without the need of low frequency magnetics (DC inductors) and; It has constant high efficiency independent of the load. The ETM converter can be implemented into a PM wind power system with smaller size, reduced weight and lower cost. As a result of our analyses, the ETM offers wind power generation technology for the reduction of the cost and size as well as the increase in performance of low power, low wind speed power generation. This project is the further theoretical/analytical exploration of the ETM converter concept in relationship to PM wind power generator applications in the 100kW and under power range. The theoretical/analytical and bench scale work focuses on simplifying the basic ETM converter topology (in terms of parts count and complexity) for the specific application of the low power PM system. The project goals and objectives were for Spellman HV will develop a 100kW prototype ETM power converter based on paralleled lower ratings converters. The proposed configuration of this prototype is a 100kW rated converter comprised of four (4) 34kW rated modules connected in parallel (the fourth converter is included to demonstrate N+1 fault tolerance). This approach is more viable as there is lower technological risk involved in developing a 34kW-rated converter than a single 100kW unit. The modular system approach should have a lower deployment and service cost over a single unit system, because of the economics of scale (smaller units at a higher volume means lower manufacturing cost) and because of improved serviceability (a non-redundant power system with one failed module will still operate at a lower power level). There is also the added benefit that greater commercial application and acceptance should be achieved by having a modular system available in which fault tolerance (N+1 or 2N) is a feature. This modular approach would allow the output power to be increased by adding more paralleled converters. Thus, the maximum output power of the overall power system is a function of the interconnection medium (the hot swap connection subsystem), rather than the ratings of a single module. The project was implemented with Spellman HV acting as the program management and production assembly and test facility; The Baker Company acting as a technical consultant and resource when required; and dtm Associates acting as the design/development resource for the hardware development of the 100kW ETM converter prototype.

In this paper, an integrated synthesis system is established to synthesize speed-independent asynchronous circuits directly from STGs with limited fanin basic gates. It combines asynchronous technology mapping and synthesis into an integrated one and thus can get the mapping solution for those whose mapping results can not be generated by previous separate mapping methods. In addition, the whole synthesis is carried out entirely on the STG level without generating the SGs and thereby preserve the problem size proportional to the number of signals. With the proposed method, STGs can be synthesized and hazard-free mapped circuits generated simultaneously in very low CPU time. Our method has been automated and applied to a large set of asynchronous benchmarks and industrial circuits.

We show that existing synthesis techniques may produce asynchronous circuits that are not initializable by gate level analysis tools even when the design is functionally initializable. Due to the absence of any initialization sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for these circuits. In this paper, we show that proper consideration of initializability during the asynchronous circuit synthesis procedure can guarantee initializable implementations. We show that the assignment of don't cares during the synthesis procedure affects the initializability of the final implementation. We present a novel implicit enumeration procedure that selectively assigns don't cares to obtain an initializable implementation. Initialization sequences are obtained as a by-product of our synthesis procedure.

In a typical digital system implemented using Orthogonal Frequency Division Multiplexing (OFDM) communication modules, the main defensive component which affects the efficiency of digital data transmission is Peak to Average Power Ratio (PAPR) and it happens in the network, because of the use of higher order linear amplifiers. The proposed method in the article emphasis on the repeated based algorithm to minimize the PAPR in low power digital communication system based OFDM network by a asymmetrical depreciation or without the loss of data symbols in bit or code rate to satisfy very minimum range of Signal to Noise Ratios (SNR). Minimum range of PAPR results the communication system to function factor of 3-3.5 dB and corresponding clipping probability of 〖10〗 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">^</sup>(-2), and with the comparison, with 5-5.5 dB equivalent to 〖10〗 ^(-4) to 〖10〗 ^(-5) resulting in.

The basic pressure housings used in all units are 24-in. OD aluminum hemisphere sets with a 1-in. wall thickness and 16,400-ft designed operating -depth. These sets are used in several different combinations and configurations as a basis for both seismic and oceanographic instrumentation capsules. Units using four-, two- and one-sphere combinations have been deployed successfully. The instrumentation includes digital data recording and an acoustical control and digital data transmission system. The free-standing ocean floor capsule has been adapted to many uses and configurations and has proved to be extremely versatile and reliable. The basic technology of these systems is developed and only waits to be employed to replace more expensive and less satisfactory methods. INTRODUCTION Increased scientific interest in phenomena occurring below the surface of the ocean has prompted expansion of the deep-sea instrument capsule program at the Institute of Geophysics and Planetary Physics, U. of California, San Diego. The basic building block of all systems is the 24-in. OD, 1-in. wall thickness aluminum pressure hemisphere rated for a 16,400-ft operating depth. These are installed in pairs with an O-ring on each side of a center plate. Center plates of one-, two- and three-coplanar instrument mounting holes have been constructed and tested as illustrated in Figs. 1 through 3. Instrumentation is typically mounted from swinging brackets split at the line of the center plate to allow access to both interior and exterior components. In multiple-sphere systems interconnecting electrical wiring is routed through small holes drilled in the center plate between instrument mounting holes. This system eliminates the need for underwater electrical connectors between housings, thus eliminating several typically more troublesome components. Any underwater electrical connectors that are employed are placed in triangular cut-outs between spheres as in Fig. 4. This affords maximum protection from accidental bumping or snagging of a connector during handling. The basic hemispherical package is used in several different combinations and configurations as a basis for both undersea seismic and oceanographic applications. THE FOUR-SPHERE CAPSULE Fig. 5 illustrates the most complex of the capsules which uses four hemisphere sets, three with coplanar instrument mounting plate and one above for an extra flotation and stability in the water. These house a long period Block-Moore vertical seismometer, a two-axis tiltmeter, a low power digital data-recording system, and a 10-channel underwater acoustic command system that includes a digital data transmission link. The data link sends 24 separate' channels of data to the surface at 100 bits/sec for storage in a decoding and memory unit. Results can be displayed individually by channel or printed out serially on a printer. The present system has a very low bit-error rate as long as position is maintained within 300 directly over the capsule.

This paper presents a modular verification approach for asynchronous circuits to address state explosion with a novel interface refinement method to reduce false counterexamples.This method borrows the idea of parallel composition, and it iteratively refines each component in a design by examining its interface interactions, and removes the behavior not synchronized with its neighbors. This method is further enhanced by synchronizing multiple components simultaneously so that inter-dependencies among components are considered. The experiments on several large asynchronous circuits show that this method efficiently removes impossible behavior from each component including ones violating correctness requirements.

Power clock generators (PCGs) are the prevalent overhead for the adiabatic systems and mutilate all the low-power advantage from the adiabatic logic part by consuming a large portion of the total power in the clock generation circuitry (Arsalan and Shams, 2005). In addition to the PCG issues, routing multiple clock phases for adiabatic circuits is not very convenient and raises a number of cost, performance and viability issues. To get rid of the problems related to clock generation and synchronous clock routing, a new solution namely asynchronous adiabatic logic (AAL) is proposed to combing the benefits of the adiabatic logic circuits with that of asynchronous logic systems. Going asynchronous not only eliminates the need of PCGs, hence all the problems associated with the generation and routing of the clocks, it also bring all the advantages intrinsically associated with an asynchronous design such as low power and reliable logical operation.

Minimizing power consumption is one of the most important objectives in VLSI design. This paper introduces a methodology for the optimization of total power consumption of template based asynchronous circuits via dual V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> assignment, dual V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> assignment and template sizing while maintaining performance requirements. The utilized circuit model is a Timed Petri-net which captures the dynamic behavior of the circuit. These three power reduction techniques are properly encoded in a quantum genetic algorithm and evaluated simultaneously. Experimental results are given for a number of 65 nm related benchmark circuits and show that this method reduces the total power by close to an order of magnitude, with no or negligible performance penalty. From the experimental results, we show that the combination of asynchronous design and three low power techniques is an effective way to achieve low power and high performance circuits.

With the increase of popularity in an asynchronous system design style, the request for asynchronous high-level synthesis tools is increasing continuously. In this paper, we suggest a new resource constrained asynchronous scheduling method which is performed through transformation of a dataflow graph (DFG). Experimental results show that the suggested scheduling method can produce a correct and efficient schedule from an initial DFG and the resulting schedule leads to a faster and more flexible asynchronous system compared to a corresponding synchronous system.

The authors evaluate their proposed asynchronous state-machine synthesis method, which uses locally synthesized clocks, on two realistic examples: a DRAM controller and a small computer systems interface controller. These circuits are designed to satisfy existing interface specifications, and are substantially larger than interfaces that have been created by competing methods, such as signal transition graph synthesis. The performance of the resulting implementations is at least as good as that of comparable synchronous implementations. >

&lt;p&gt;&lt;em&gt;The Indonesian University of Education faced project delays that had an impact on the budget and timing of the Postgraduate Building's development. The UPI Postgraduate Building is being constructed using traditional methods, which results in a lengthy amount of work. The aforesaid issue might have a solution in the modular approach. The modular approach can swiftly meet significant customer demands since it has a production technique for creating components that are mass-produced. The conventional method's implementation costs and timeline are being contrasted with the modular method's implementation costs and timeline. The cost and construction time of traditional walls and modular walls which use precast concrete materials and lightweight concrete panels are compared for wall components. To make the optimal decision, the analysis was done using the comparison technique and the cost-effectiveness analysis approach. From the results of the analysis, the use of precast concrete and lightweight concrete panels experienced cost inefficiencies of 17.92% and 11.75% but were able to save time 62.03% and 34.78% respectively. Based on the Cost Effectiveness Analysis, an alternative material that was a more cost-effective choice was precast concrete walls.&lt;/em&gt;&lt;/p&gt;

This paper presents a compiler from a standard Hardware Description Language (Verilog HDL) to an asynchronous Control Unit and a synchronous Data Path. The Control Unit, specified as a Signal Transition Graph, can be implemented using research-oriented asynchronous synthesis tools. The Data Path, specified using the Synthesizable Subset of Verilog, can be implemented using state-of-the-art commercial synchronous synthesis tools. Our compiler integrates in a fully automated manner source parsing, control/data splitting, managing the design and inserting matched delays for data bundling constraints. It can be used to produce asynchronous designs in an Application Specific Integrated Circuit design style, since the result is a netlist of standard cells ready for physical design. We describe a simple example of compilation and its results, and we discuss some outstanding issues in the domain of asynchronous Control Unit synthesis.

In recent years, consumer electronic devices have been expanding their application domains from traditional consumer electronic devices such as cellular phones, PDAs(Personal Digital Assistants), PMPs(Portable Multimedia Players), Navigation, to Next Generation Personal Computers(NGPCs) such as eating consumer electronic devices, implanted consumer electronic devices, wearable consumer electronic devices. A wearable consumer electronic device is a computer that is subsumed into the personal space of the user, controlled by the user, and is always on and always accessible. Therefore, among the most salient aspect of wearable consumer electronic devices should be small form factor and long battery lifetime. In this paper, we propose a novel low-power real-time operating system (RTOS) specialized for the ARC(Actual Remote Control). An ARC is a wearable wristwatch-type remote controller; it also can serve as a universal remote control for various consumer electronic devices. The proposed RTOS has about 9KB footprints and is equipped with low-power techniques composed of the dynamic power management and the device power management. Experimental results with wearable application show that we can save energy up to 47 % using the proposed low-power techniques.

Synthesis of straight-chain C49H100 alkane using a modular splicing strategy