An integrated synthesis system for speed-independent asynchronous circuits

We describe a technique to estimate the energy consumed by speed-independent asynchronous (clock-less) control circuits. Because speed-independent circuits are hazard-free under all possible combinations of gate delays, we prove that an accurate estimate of their energy consumption is independent of relative component gate delays and can be determined by simulating only a small number of input patterns proportional to the size of the circuit's Signal Transition Graph specification. Specifically, we calculate the average energy per external signal transition consumed by a circuit. This can be used to compare the energy consumption between two different circuit implementations of the same specification, to calculate average energy for a given high-level operation, and to provide average circuit power when combined with delay information.

Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an efficient modular partitioning approach for asynchronous circuit synthesis. This approach partitions a large circuit specification into smaller and manageable modules that drastically reduces the synthesis complexity. Experimental results with a large number of practical asynchronous benchmarks are presented. They show that, compared to the existing techniques, this modular partitioning method achieves many orders of magnitude of performance improvement in terms of computing time, in addition to a reduced implementation area. It offers a practical solution for complex asynchronous circuit design problems.

We describe sufficient conditions for the correctness of speed-independent asynchronous circuits. The circuit specifications considered are determinate, allowing input choice but not output choice (arbitration). The circuit implementations considered are networks of single-output basic gates. A circuit is defined to be correct if it is hazard-free and complex-gate equivalent to its specification. We show that a circuit is hazard-free if and only if all of its signals are monotonic and acknowledged. This result provides a useful tool for formal reasoning about the correctness of circuits and synthesis techniques. Cubes that approximate sets of reachable circuit states can be used to give sufficient conditions for monotonicity and acknowledgement. These sufficient conditions are the basis of efficient synthesis and verification algorithms.

Faster than at-speed testing provides an effective way to detect small delay defects (SDDs). It requires test patterns to be delicately classified into groups according to the delay of sensitized paths. Each group of patterns is applied at certain frequency. In this paper, we propose to generate tests for faster than at-speed testing using path delay fault (PDF) model and single path sensitization criterion. An effective path selection and grouping method is introduced, which could quickly and accurately identify paths whose delay falls into a given delay span. Several techniques are used to improve the efficiency of the testable path selection procedure. Experimental results on ISCAS'89 benchmark circuits show that the proposed method could achieve high transition fault coverage and high test quality of SDDs with low CPU time.

PurposePower consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits.Design/methodology/approachIn this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment.FindingsExperimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits.Originality/valueThe proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

Semiconductor technologies bring the possibility of embedding billions of components in a chip, allowing the design of complex integrated circuits. However, such levels of integration are not free and delay uncertainties grow steadily, which is increasingly challenging. Quasi-delay-insensitive (QDI) design promises to cope with such challenges, being less timing constrained than synchronous or bundled-data designs. However, two barriers to its wider adoption are: 1) missing methods to automatically implement QDI circuits and 2) enabling QDI semi-custom design. This paper proposes a new QDI design method that extends the null convention logic (NCL) asynchronous template. Also, it describes an associated semi-custom design flow for the extended template, which uses conventional electronic design automation tools to synthesize QDI circuits down to layout. The method enables using the full power of synthesis and optimization commercial tools. Illustrating this, the ISCAS85 benchmarks take 35%–43% less gates to implement, compared with conventional, pattern-based NCL design. A comparison with the Uncle tool provides indication that the proposed method is indeed a flexible and powerful approach to design asynchronous QDI circuits. Lastly, 16-b multiplier designed with the method until the layout level exhibits 170%–240% larger operations/Watt compared with an equivalent NCL design, and an almost 400% better operations/mm2 figure.

Previous computer-aided lung cancer image classification methods are all cost-blind, which assume that the misdiagnosis (categorizing a cancerous image as a normal one or categorizing a normal image as a cancerous one) costs are equal. In addition, previous methods usually require experienced pathologists to label a large amount of images as training samples. To this end, a novel transductive cost-sensitive method is proposed for lung cancer image classification on needle biopsies specimens, which only requires the pathologist to label a small amount of images. The proposed method analyzes lung cancer images in the following procedures: (i) an image capturing procedure to capture images from the needle biopsies specimens; (ii) a preprocessing procedure to segment the individual cells from the captured images; (iii) a feature extraction procedure to extract features (i.e. shape, color, texture and statistical information) from the obtained individual cells; (iv) a codebook learning procedure to learn a codebook on the extracted features by adopting k-means clustering, which aims to represent each image as a histogram over different codewords; (v) an image classification procedure to predict labels for testing images using the proposed multi-class cost-sensitive Laplacian regularized least squares (mCLRLS). We evaluate the proposed method on a real-image set provided by Bayi Hospital, which contains 271 images including normal ones and four types of cancerous ones (squamous carcinoma, adenocarcinoma, small cell cancer and nuclear atypia). The experimental results demonstrate that the proposed method achieves a lower cancer-misdiagnosis rate and lower total misdiagnosis costs comparing with previous methods, which includes the supervised learning approach (kNN, mcSVM and MCMI-AdaBoost), semi-supervised learning approach (LapRLS) and cost-sensitive approach (CS-SVM). Meanwhile, the experiments also disclose that both transductive and cost-sensitive settings are useful when only a small amount of training images are available.

We show that existing synthesis techniques may produce asynchronous circuits that are not initializable by gate level analysis tools even when the design is functionally initializable. Due to the absence of any initialization sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for these circuits. In this paper, we show that proper consideration of initializability during the asynchronous circuit synthesis procedure can guarantee initializable implementations. We show that the assignment of don't cares during the synthesis procedure affects the initializability of the final implementation. We present a novel implicit enumeration procedure that selectively assigns don't cares to obtain an initializable implementation. Initialization sequences are obtained as a by-product of our synthesis procedure.

This paper presents a time-efficient method for the decomposition and resynthesis of speed-independent (SI) circuits. Given the specification of an SI circuit, our method first generates its standard C implementation. Then, the combinational decomposition is performed to decompose each high-fanin gate that does not exist in the gate library into some available low-fanin gates. The time efficiency of our method is achieved in two ways. First, the signal transition graph (STG), whose complexity is polynomial in the worst case, is adopted as our input specification. Second, to reduce the resynthesis cycles, which constitute a major part of the run time, our method first investigates the hazard-free decomposition of each high-fanin gate without adding any signals. Then, for those gates that cannot be decomposed hazard free, two signal-adding methods constructed at the STG level are developed for resynthesis. This decomposition and resynthesis process is iterated until all high-fanin gates are successfully decomposed or no solution can be found. Several experiments on asynchronous benchmarks show that our method largely reduces run time with only a little more area expense when compared with previous work.

In this article, a brand new method of determining deadlock is presented. Most previous deadlock detection methods are algorithmic in the sense that they usually leverage some forms of Resource Allocation Graph (RAG) representations and then algorithms are devised to manipulate such representations in order to detect deadlock using information contained in the graph. Different from all previous methods, the proposed method actualizes the RAG with a digital circuit and uses it as a token-transmitting network. By supplying special input signals (tokens) to the network and observing the output tokens from the network, it is easier to identify which process nodes are reachable from each resource node in the graph. Using the reachability information, deadlock can be detected immediately. The time required to obtain the reachability information is determined by how fast the combinational circuit operates. Compared with previous algorithmic methods, the proposed deadlock detection can be deemed instant. We show that the proposed method is an order of magnitude faster than the previous fastest hardware mechanism and several orders of magnitude faster than traditional software-based algorithms.

Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward way is to structurally map the gates in a synchronous netlist to their functionally equivalent modules which use delay-insensitive codes. Different trade-offs exist in previous methods between the overheads of the implementations and their robustness. The aim of this paper is to optimise the area of asynchronous circuits using partial acknowledgement concept. We employ this concept in two design flows, which are implemented in a software tool to evaluate the efficiency of the method. The benchmark results show the average reduction in area by 28% and in the number of inter-functional module wires that require timing verification by 67%, compared to NCL-X

ABSTRACTA case study on the source separation of municipal solid waste (MSW) was performed in Changsha, the capital city of Hunan Province, China. The objective of this study is to analyze the effects of different separation methods and compare their effects with citizens’ attitudes and inclination. An effect evaluation method based on accuracy rate and miscellany rate was proposed to study the performance of different separation methods. A large-scale questionnaire survey was conducted to determine citizens’ attitudes and inclination toward source separation. Survey result shows that the vast majority of respondents hold consciously positive attitudes toward participation in source separation. Moreover, the respondents ignore the operability of separation methods and would rather choose the complex separation method involving four or more subclassed categories. For the effects of separation methods, the site experiment result demonstrates that the relatively simple separation method involving two categories (food waste and other waste) achieves the best effect with the highest accuracy rate (83.1%) and the lowest miscellany rate (16.9%) among the proposed experimental alternatives. The outcome reflects the inconsistency between people’s environmental awareness and behavior. Such inconsistency and conflict may be attributed to the lack of environmental knowledge. Environmental education is assumed to be a fundamental solution to improve the effect of source separation of MSW in Changsha. Important management tips on source separation, including the reformation of the current pay-as-you-throw (PAYT) system, are presented in this work.Implications: A case study on the source separation of municipal solid waste was performed in Changsha. An effect evaluation method based on accuracy rate and miscellany rate was proposed to study the performance of different separation methods. The site experiment result demonstrates that the two-category (food waste and other waste) method achieves the best effect. The inconsistency between people’s inclination and the effect of source separation exists. The proposed method can be expanded to other cities to determine the most effective separation method during planning stages or to evaluate the performance of running source separation systems.

Controller synthesis using data-driven clocks

In this chapter, we present applications of regions and elementary (or quasielementary) net synthesis for the design of speed independent circuits. Asynchronous circuit design is a wide and complex field that encompasses other topics than Petri nets. We refer the reader to the book [46] for a complete presentation of this field. We will limit ourselves to assessing the roles played by regions and net synthesis for solving the Complete State Coding problem (CSC). This crucial problem motivated the implementation of a net synthesis procedure in Petrify, a general design tool for asynchronous circuits presented in [46]. It must be acknowledged that different methods based on net unfoldings and SAT solvers are now preferred over net synthesis for solving the CSC problem.

Estimation of asynchronous circuit performances, such as speed, is one of the major issues that make that design style still less popular than it deserves to be. Evaluating the worst case delays in the paths of an asynchronous circuit using a simple logic simulator would be very useful in overcoming this problem. In this paper a method for timing analysis of the asynchronous non-sequential circuits using a VHDL simulator is presented. With an appropriate extension of the standard logic simulation process, all worst case delays for all paths in a digital circuit with only one run of the simulation can be obtained. High levels of accuracy are achieved using different gate modelling and statistical analysis of the results. Due to the lack of asynchronous benchmark circuits, the method is verified on a set of asynchronous circuit selected by the authors.