Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing

From the Publisher: This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world’s leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cache memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cach memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

This book covers the design of next generation microprocessors in deep submicron CMOS technologies. The chapters in Design of High Performance Microprocessor Circuits were written by some of the world's leading technologists, designers, and researchers. All levels of system abstraction are covered, but the emphasis rests squarely on circuit design. Examples are drawn from processors designed at AMD, Digital/Compaq, IBM, Intel, MIPS, Mitsubishi, and Motorola. Each topic of this invaluable reference stands alone so the chapters can be read in any order. The following topics are covered in depth: Architectural constraints of CMOS VLSI design Technology scaling, low-power devices, SOI, and process variations Contemporary design styles including a survey of logic families, robust dynamic circuits, asynchronous logic, self-timed pipelines, and fast arithmetic units Latches, clocks and clock distribution, phase-locked and delay-locked loops Register file, cache memory, and embedded DRAM design High-speed signaling techniques and I/O design ESD, electromigration, and hot-carrier reliability CAD tools, including timing verification and the analysis of power distribution schemes Test and testability Design of High-Performance Microprocessor Circuits assumes a basic knowledge of digital circuit design and device operation, and covers a broad range of circuit styles and VLSI design techniques. Packed with practical know-how, it is an indispensable reference for practicing circuit designers, architects, system designers, CAD tool developers, process technologists, and researchers. It is also an essential text for VLSI design courses.

PurposePower consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits.Design/methodology/approachIn this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment.FindingsExperimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits.Originality/valueThe proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

Starting from deep submicron technologies (< 0.13μm), and even stronger in nanometer technologies, static power consumption, due to leaky “off” transistors, is becoming a non-negligible contributor to the total power dissipation. Under this condition, the total power optimization problem changes considerably. The high parallelization approach commonly used today to increase performances, will soon result in power ineffcient designs. Indeed, the static power consumption of the large number of rarely used transistors will highly penalize the total power consumption. The purpose of this thesis is to investigate the influence of static power on the design methodologies for low power. In particular, the effects of architectural as well as technology modifications are explored. The use of technology as an optimization parameter has become possible in recent technologies. In fact, they offer different threshold voltages, each one showing a different trade-off between speed and leakage current. In this work, two different frameworks are considered. In the first one, both the supply voltage and the transistor threshold voltage are freely tunable parameters. This is the most general case and corresponds to the situation where the designer has the largest freedom. In the latter framework, we assume that the designer cannot change the supply voltage nor the transistor threshold voltage and they are hence considered constants. This case corresponds to the most common one, where the designer has a supply voltage and a technology type (and hence a threshold voltage) fixed by the application and by the devices the circuit has to interface. In both cases, lot of efforts have been put to the development of a handy way to rapidly estimate the total power consumption and consequently easily compare different architectural/technology variants at the early stages of development. Examples, based on multipliers, are used extensively in the whole thesis and, at the end, the presented theory is applied to a real circuit implemented in a 90nm technology by ST Microelectronics. Measurements show a very large variability of the static power over 16 dies manufactured on the same wafer. For instance, the highest static power consumption at nominal condition (Vdd=1V, f=62.5MHz) over the lowest one corresponds to more than a factor of 2.5. Measured data also report multipliers able to work at 210mV for a frequency of 1MHz!

In order to find the optimal feature subset for target recognition in foliage environment, a novel feature selection method based on quantum genetic algorithm (QGA) is proposed in this paper. The real data used to identify the targets were collected by ultra-wideband (UWB) radar system. Support vector machine (SVM) classifier is adopted to evaluate the proposed algorithm. The experimental results indicate that QGA can achieve higher accuracy of target recognition with fewer features when face with the feature selection problem. Also, the comparison between the proposed and the traditional genetic algorithm (GA)-based method will be discussed. According to the obtained results, the method presented in this paper is more effective for target identification.

In real-time image and video processing boards, power, speed, and area are the most often used measures for determining the performance of motion imagery applications. Due to technological advancement, power consumption has gained major attention in real-time image processing ability compared to speed. The increase in on-chip temperature due to larger power consumption has resulted in reduced operating life of chip and battery-driven devices. In this work, a new logic family has been introduced i.e., dual-mode logic (DML), which provides flexibility between the optimization of energy and delay (E-D optimization). This gate can be switched between two modes of operation that is a static mode (CMOS-like mode), which provides low power consumption and dynamic mode, which provides high speed. Recently, power leakage has become a dominant problem due to continuous data transfer among a large number of connected devices. Thus, to reduce power leakage, a self-controllable voltage level (SVL) power reduction technique is used along with DML logic. In the SVL technique, a maximum dc voltage is provided to the active load circuit on-demand or decrease the dc supplied to the load circuit in the standby mode. Integrating DML with the SVL technique reduces power consumption as well as leakage power. A 4-bit RCA, 8-bit RCA, and 16-bit RCA are used for verifying the proposed method and comparison of performance parameters is done with a conventional circuit. Complete circuit implementation and simulation are carried out in TANNER EDA version 13 tools with operating voltage of 1 V. The proposed system is further applied to real-time image, and we obtain the finest resolution level with minimum power consumption.

Aiming at the disadvantages of the fixed rotation angle in quantum genetic algorithm (QGA), in this paper, the particle swarm optimization (PSO) was used to update the angle of quantum rotation gate in stead of the old one that locates the angle of quantum rotation gate by a designed query table. According to the experimental results, the novel quantum genetic algorithm (NQGA) with new updating method has got a higher global search capability than common QGA. The NQGA was used to the load distribution optimization of tandem cold rolling. The comparison data show that the NQGA is an effective method for load distribution optimization of tandem cold rolling.

In this paper, we extend the verification method based on the failure semantics of process algebra and the resulting trace theory by Dill et al. for bounded delay asynchronous circuits. We define a timed conformance relation between trace structures which allows to express both safety and responsiveness properties. In our approach, bounded delay circuits as well as their real-time properties are modelled by time Petri nets. We give an explicit state-exploration algorithm to determine whether an implementation conforms to a specification. Since for IO-conflict free specifications the conformance relation is transitive, this algorithm can be used for hierarchical verification of large asynchronous circuits. We describe the implementation of our method and give some experimental results which demonstrate its efficiency.KeywordsTrace TheoryTime Petri NetsFailure AnalysisConformance CheckingState Space ExplorationAsynchronous CircuitsHardware VerificationDelay AnalysisReal Time SystemsComputer Aided Verification

In this paper, we discuss physical-layer network coding (PLNC) in the two-way decode-forward (DF) relay to obtain total minimum power consumption (MPC) for the entire transmission process. The MPC and power allocation scheme for each node are obtained under a predetermined constraint of outage probability threshold in a Rayleigh fading channel environment. Numerical experimental results confirm that the proposed MPC scheme achieves much lower power consumption ratio than the existing schemes without PLNC on the condition of the same system outage guarantee.

Data is generated enormously today and to process this we need large memories with high speed and optimized power consumption. Conventional DRAM based system which were used as memory in computing systems for several decades are facing challenges in scalability and power consumption. In this regard non-volatile memories with excellent scalability and minimal power consumption are studied extensively. This paper analyzes the impact of introducing SOT-MRAM a non-volatile main memory device as an alternative to DRAM. Experimental results show an average power reduction of 46.09% with an increase in performance up to 30% when DRAM is replaced with SOT-MRAM for embedded system workloads.

On the basis of the operation characteristics of NULL Convention Logic (NCL) circuit and popular block cipher algorithms, this paper proposes a model of NCL circuits computing, which targeted at characteristic of block cipher, and then maps Rijndael algorithm on the model based on NCL circuit by two ways. The circuit model has been validated in Balsa system, and synthesized with Balsa using 1 mum example NCL Cell Library. The experiment results indicate that the circuit model has high flexibility for block cipher algorithms.

CMOS technology scaling has paved the way for a faster and more complex integration. Low-power techniques have become crucial because of the demand for low power consumption and high speed. The main objective of this research is to utilize low-power techniques to implement a 4-bit barrel shifter that can shift or rotate data using any number of bits within a single cycle. Gate Diffusion Input (GDI), modified GDI, and full-swing GDI logic have been employed to implement a 2:1 multiplexer, among which the modified GDI-based multiplexer stands out because of its minimal power consumption. Consequently, a 4-bit barrel shifter is implemented using a modified GDI-based multiplier. All designs and simulations were performed using the Cadence Virtuoso tool in UMC 65 nm technology. This technology enables the accurate analysis and assessment of the designed barrel shifter, considering the characteristics and limitations of the 65 nm process. This study focused on leveraging low-power techniques to implement a 4-bit barrel shifter to address the industry's demand for power-efficient solutions. The modified GDI-based multiplexer is a promising choice that provides a balance between low power consumption and high performance. The use of advanced design tools and selected technology further ensures accurate simulations and evaluations of the proposed design.

Robots have to be able to move on different surfaces while ensuring the motion feasibility. One of the issues that have always attracted the attention of researchers in this field is optimization of power consumption along with maximum stability during the motion. Lots of basic gait parameters can be expressed by a planned seven-linked bipedal robot. In this study, parameter optimization being used in order to optimize the problem of motion obtained in a way that maximizing stability of robot and minimizing energy and also preserving its stability. Zero moment point scale is being used to calculate the stability of a robot. Experimental tests were performed for motion analysis of walking correctly and the results were validated. Finally, due to the presented model and optimized issue and predicted path, the robot can move like a person in a way that has maximum stability along with minimum power consumption. Comparison of experimental results versus presented model was used in each step to validate the accuracy of the proposed method.

Many techniques for power reduction in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care conditions. In this article we propose a systematic approach to maximize the effectiveness of these techniques by generating power-friendly RTL descriptions in behavioral synthesis. This is done using operation gating , that is, explicitly adding a predicate to an operation based on its observability condition, so that the operation, once identified as unobservable at runtime, can be avoided using RTL power optimization techniques such as clock gating. We first introduce the concept of behavior-level observability and its approximations in the context of behavioral synthesis. We then propose an efficient procedure to compute an approximated behavior-level observability of every operation in a dataflow graph. Unlike previous techniques which work at the bit level in Boolean networks, our method is able to perform analysis at the word level, and thus avoids most computation effort with a reasonable approximation. Our algorithm exploits the observability-masking nature of some Boolean operations, as well as the select operation, and allows certain forms of other knowledge to be considered for stronger observability conditions. The approximation is proved exact for (acyclic) dataflow graphs when non-Boolean operations other than select are treated as black boxes. The behavior-level observability condition obtained by our analysis can be used to guide the operation scheduler to optimize the efficiency of operation gating. In a set of experiments on real-world designs, our method achieves an average of 33.9% reduction in total power; it outperforms a previous method by 17.1% on average and gives close-to-optimal solutions on several designs. To the best of our knowledge, this is the first time behavior-level observability analysis and optimization are performed during behavioral synthesis in a systematic manner. We believe that our idea can be applied to compiler transformations in general.