Verification of Bounded Delay Asynchronous Circuits with Timed Traces

To formally verify the real-time system using model checking technique, two necessary elements are required, the real-time system model and its expected real-time properties. In order to specify these real-time properties, an appropriate extended logic system, to cope with quantitative of time constraints is needed. We select one of the most popular real-time logic systems, called Metric Temporal Logic (MTL) to specify our mentioned real-time properties. However, the real-time properties defined in MTL are still not relevant to SPIN model checker. In this paper, we propose a novel scheme to translate the basic MTL formulas into Promela and LTL formulas as to be relevantly used in SPIN, in terms of Promela’s inline definitions and macro commands. The punctuality of the formulas is preserved during the translation. Practically, the basic timing constraints eventually and always operators of MTL are focused, and the translation of MTL formulas of the real-time safety property patterns is demonstrated.

Minimizing power consumption is one of the most important objectives in VLSI design. This paper introduces a methodology for the optimization of total power consumption of template based asynchronous circuits via dual V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> assignment, dual V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> assignment and template sizing while maintaining performance requirements. The utilized circuit model is a Timed Petri-net which captures the dynamic behavior of the circuit. These three power reduction techniques are properly encoded in a quantum genetic algorithm and evaluated simultaneously. Experimental results are given for a number of 65 nm related benchmark circuits and show that this method reduces the total power by close to an order of magnitude, with no or negligible performance penalty. From the experimental results, we show that the combination of asynchronous design and three low power techniques is an effective way to achieve low power and high performance circuits.

With the introduction of hierarchization of computer integrated manufacturing (CIM), autonomous decentralization appears important. The paper attempts to report the hierarchical system structures and algorithms employed in a simulation system based on the optimum coupling and selection of the dispatching rules as a part of the software solution. Further, as a possible control method of such systems, the paper discusses the applications of timed Petri nets as an analytical tool for observing the behavior of the asynchronous parallel processing systems. >

Asynchronous circuits have potential advantages of higher speed and lower power consumption compared to their synchronous counterparts, but their poor CAD support is a major issue limiting adoption. In this paper, we present an integrated timing and power analysis engine capable of handling large asynchronous circuits. For timing, we introduce the notion of performance and correctness slack for asynchronous circuits; for power, we compute both the static and dynamic components. We provide a hierarchical approach to constructing the event-dependency graph, and use the Galois framework for parallelization to achieve fast runtime. The net result is Cyclone, a fast and accurate engine for both static timing and power analysis of asynchronous circuits.

Consider the fundamental generalized predictive control is an explicit algorithm, which needs solving the Diophantine equation and the inverse of matrices, the on-line computational quantity is big and the real-time property is poor. This paper puts forward a generalized predictive PID controller to the second-order time delay system commonly used in industry, which makes the control process more convenient and clear. Besides, a direct generalized predictive control method is presented in this paper, which has fewer requirements for modeling and can adaptively adjust the controller's parameters based on generalized estimate errors. The controller's parameters are identified directly instead of using the explicit algorithm, and the online computing time is shortened. At last, the simulation in MATLAB demonstrates the effectiveness of this method.

Speed-independent circuits offer a potential solution to the timing problems of VLSI. In this book David Dill develops and implements a theory for practical automatic verification of these control circuits. He describes a formal model of circuit operation, defines the proper relationship between an implementation and its specification, and constructs a computer program that can check this relationship. Asynchronous or speed-independent circuit design has gained renewed interest in the VLSI community because of the possibilities it provides for dealing with problems that arise with the increasing complexity of VLSI circuits. Speed-independent circuits offer a way around such phenomena as clock skew, which can be a serious obstacle in the design of large systems. They can expedite circuit design by reducing design time and simplifying the overall process. A major challenge to the successful utilization of speed-independent circuits is correctness. The verification method described here insures that a design is correct and because it can be automated it is a significant advantage over manual verification. Dill proposes two distinct theories - prefix-closed trace structures, which can model and specify safety properties, and complete trace structures, which can also deal with liveness and fairness properties. Trace Theory for Automatic Hierarchical Verification of Speed Independent Circuits is a 1988 ACM Distinguished Dissertation

PurposePower consumption is a top priority in high-performance asynchronous circuit design today. The purpose of this study is to provide a spatial correlation-aware statistical dual-threshold voltage design method for low-power design of template-based asynchronous circuits.Design/methodology/approachIn this paper, the authors proposed a statistical dual-threshold voltage design of template-based asynchronous circuits considering process variations with spatial correlation. The utilized circuit model is an extended Timed Petri-Net which captures the dynamic behavior of the asynchronous circuit with statistical delay and power values. To have a more comprehensive framework, the authors model the spatial correlation information of the circuit. The authors applied a genetic optimization algorithm that uses a two-dimensional graph to calculate the power and performance of each threshold voltage assignment.FindingsExperimental results show that using this statistically aware optimization, leakage power of asynchronous circuits can be reduced up to 3X. The authors also show that the spatial correlation may lead to large errors if not being considered in the design of dual-threshold-voltage asynchronous circuits.Originality/valueThe proposed framework is the scheme giving a low-power design of asynchronous circuits compared to other schemes. The comparison exhibits that the proposed method has better results in terms of performance and power. To consider the process variations with spatial correlation, the authors apply the principle component analysis method to transform the correlated variables into uncorrelated ones.

We describe a methodology for analyzing timed systems symbolically. Given a formula representing a set of timed states, we describe howto determine a new formula that represents the set of states reachable by taking a discrete transition or by advancing time. The symbolic representations are given as formulae expressed in a simple first-order logic over constraints of the form x-y ? d which can be combined with Boolean operators and existentially quantified. The main contribution is a way of advancing time symbolically essentially by quantifying out a special variable z which is used to represent the current zero point in time. We describe how to model asynchronous circuits using timed guarded commands and provide examples that demonstrate the potential of the symbolic analysis.

The self-timed (or asynchronous) approach to circuit design has demonstrated benefits in a number of different areas for its low energy consumption, high operating speed, composability, and modularity. Nonetheless, the asynchronous paradigm exposes challenges that are not found in the synchronous (or clock-driven) paradigm. For the verification task, a challenge emerges from the large number of potential operational interleavings exhibited in the asynchronous paradigm. Simply exploring all interleavings is, in general, intractable because the number of interleavings can grow exponentially. This dissertation focuses on developing scalable methods that are capable of reasoning effectively about the interleaving problem exhibited in self-timed systems. We specify and verify finite-state-machine representations of self-timed circuit designs using the DE system, a formal hardware description language defined using the ACL2 theorem-proving system. We apply a link-joint paradigm to model self-timed circuits as networks of channels that communicate with each other locally via handshake protocols. This link-joint model has been shown to be a universal model for various self-timed circuit families. In addition, this model has a clean formalization in the ACL2 logic and provides a protocol level that abstracts away timing constraints at the circuit level. Unlike many efforts for validating timing and communication properties of self-timed systems, we are interested in verifying functional properties. Specifically, we verify the functional correctness of self-timed systems in terms of relationships between their input and output sequences. To mitigate the consideration of all interleavings simultaneously, we address the verification problem hierarchically and avoid exploring the internal structures of verified submodules as well as their operational interleavings. The input-output relationship of a verified submodule is determined based on the communication signals at the submodule's input and output ports, while abstracting away all execution paths internal to that submodule.

Automatic verification of implementations against their specifications in the design hierarchy is largely based on state machine comparison. This paper presents a simple technique that exploits information about correspondence between registers in the data path to enable abstraction of data path registers and make automatic verification of circuits with large date paths tractable. Correspondence between registers which encode the control states is not required. This generality enables efficient verification of large circuits with data paths structured differently, as well as verification against specifications devoid of structural information. Results are presented for the verification of realistic circuits at different levels in the design hierarchy.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The specification and design of hard real-time systems using timed and temporal petri nets

This paper presents a modular verification approach for asynchronous circuits to address state explosion with a novel interface refinement method to reduce false counterexamples.This method borrows the idea of parallel composition, and it iteratively refines each component in a design by examining its interface interactions, and removes the behavior not synchronized with its neighbors. This method is further enhanced by synchronizing multiple components simultaneously so that inter-dependencies among components are considered. The experiments on several large asynchronous circuits show that this method efficiently removes impossible behavior from each component including ones violating correctness requirements.

Asynchronous circuits are crucial in designing low power and high performance digital systems. In this paper, we present an efficient modular partitioning approach for asynchronous circuit synthesis. This approach partitions a large circuit specification into smaller and manageable modules that drastically reduces the synthesis complexity. Experimental results with a large number of practical asynchronous benchmarks are presented. They show that, compared to the existing techniques, this modular partitioning method achieves many orders of magnitude of performance improvement in terms of computing time, in addition to a reduced implementation area. It offers a practical solution for complex asynchronous circuit design problems.

This paper presents a methodology to incorporate hierarchy in the design verification process of large full custom digital CMOS circuits including the effects of statistical process variation and variation in external parameters like temperature and supply voltage. Behavioural models are used to describe sub-circuits on a high level of abstraction. Statistical tolerance information from the circuit level is mapped onto the behavioural models. By means of a case study on a large full custom design we show that this design verification methodology can be very efficient.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP