Timed Verification of Asynchronous Circuits

The self-timed (or asynchronous) approach to circuit design has demonstrated benefits in a number of different areas for its low energy consumption, high operating speed, composability, and modularity. Nonetheless, the asynchronous paradigm exposes challenges that are not found in the synchronous (or clock-driven) paradigm. For the verification task, a challenge emerges from the large number of potential operational interleavings exhibited in the asynchronous paradigm. Simply exploring all interleavings is, in general, intractable because the number of interleavings can grow exponentially. This dissertation focuses on developing scalable methods that are capable of reasoning effectively about the interleaving problem exhibited in self-timed systems. We specify and verify finite-state-machine representations of self-timed circuit designs using the DE system, a formal hardware description language defined using the ACL2 theorem-proving system. We apply a link-joint paradigm to model self-timed circuits as networks of channels that communicate with each other locally via handshake protocols. This link-joint model has been shown to be a universal model for various self-timed circuit families. In addition, this model has a clean formalization in the ACL2 logic and provides a protocol level that abstracts away timing constraints at the circuit level. Unlike many efforts for validating timing and communication properties of self-timed systems, we are interested in verifying functional properties. Specifically, we verify the functional correctness of self-timed systems in terms of relationships between their input and output sequences. To mitigate the consideration of all interleavings simultaneously, we address the verification problem hierarchically and avoid exploring the internal structures of verified submodules as well as their operational interleavings. The input-output relationship of a verified submodule is determined based on the communication signals at the submodule's input and output ports, while abstracting away all execution paths internal to that submodule.

A combined delay model to manipulate the variance of the delay time of logic elements and a timing verification method based on the theory of regular expressions are presented. Emphasis is placed on the hazard detection problem and the verification of asynchronous circuits. The effectiveness of the method with medium sized circuits including about 100 elements is shown.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper, we extend the verification method based on the failure semantics of process algebra and the resulting trace theory by Dill et al. for bounded delay asynchronous circuits. We define a timed conformance relation between trace structures which allows to express both safety and responsiveness properties. In our approach, bounded delay circuits as well as their real-time properties are modelled by time Petri nets. We give an explicit state-exploration algorithm to determine whether an implementation conforms to a specification. Since for IO-conflict free specifications the conformance relation is transitive, this algorithm can be used for hierarchical verification of large asynchronous circuits. We describe the implementation of our method and give some experimental results which demonstrate its efficiency.KeywordsTrace TheoryTime Petri NetsFailure AnalysisConformance CheckingState Space ExplorationAsynchronous CircuitsHardware VerificationDelay AnalysisReal Time SystemsComputer Aided Verification

ObjectivesThe primary purpose of this meta-analysis was to determine whether statin usage could reduce the risk of glucocorticoid-related osteonecrosis in animal models.MethodsA systematic literature search up to May 2015 was carried out using the PubMed, Ovid, EBM reviews, ISI Web of Science, EBSCO, CBM, CNKI databases with the term and boolean operators: statins and osteonecrosis in all fields. Risk ratio (RR), as the risk estimate of specific outcome, was calculated along with 95% confidence intervals (CI). The methodological quality of individual studies was assessed using a quantitative tool based on the updated Stroke Therapy Academic Industry Roundtable (STAIR) recommendations.ResultsA total of 11 eligible studies were included according to predetermined criteria. The pooled data demonstrated that animals with statin usage, either alone or combined with other treatments, were at a decreased risk of developing glucocorticoid-related osteonecrosis (RR = 2.06, 95% confidence interval (CI) 1.71 to 2.50). Moreover, subgroup analysis revealed that compared with statins alone, statins combined with other treatments significantly decreased the risk of osteonecrosis (RR = 1.23, 95% CI 1.02 to 1.47). However, we could find no significant risk difference for different gender, or for different time points.ConclusionsThe present study suggests that statins combined with other treatments are efficient in preventing the development of glucocorticoid-related osteonecrosis in animals. These results might shed light on clinical practice when glucocorticoids are prescribed, and could be further investigated in high-quality clinical trials.Cite this article: Z. Yang, H. Liu, D. Li, X. Xie, T. Qin, J. Ma, P. Kang. The efficacy of statins in preventing glucocorticoid-related osteonecrosis in animal models: A meta-analysis. Bone Joint Res 2016;5:393–402. DOI: 10.1302/2046-3758.59.2000500.

In many scenarios, a patient in medical research is treated as a statistical unit. However, in some scenarios, we are interested in treating aggregate data as a statistical unit. In such situations, each set of aggregated data is considered to be a concept in a symbolic representation, and each concept has a hyperrectangle or multiple points in the variable space. To construct a tree-structured model from these aggregate survival data, we propose a new approach, where a datum can be included in several terminal nodes in a tree. By constructing a model under this condition, we expect to obtain a more flexible model while retaining the interpretive ease of a hierarchical structure. In this approach, the survival function of concepts that are partially included in a node is constructed using the Kaplan-Meier method, where the number of events and risks at each time point is replaced by the expectation value of the number of individual descriptions of concepts. We present an application of this proposed model using primary brain tumor patient data. As a result, we obtained a new interpretation of the data in comparison to the classical survival tree modeling methods.

Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits

An algebraic methodology based on Characteristic Functions (CFs) and allowing to compare switch-level circuits with higher-level specifications is presented.

This paper presents an asynchronous logic high data rate IR-UWB transmitter operating with a single 31.25 MHz reference that robustly synthesizes 1 GHz rate pulses to enable sub-meter range neural data transmission. It is designed for a low power CMOS-based implantable electrode array and operates with a master-slave PLL cascade and a simple static CMOS logic combining. The master PLL consumes a simulated 1 mW power, and locking is based on the evolution of three non-overlapping feedback loops whose switching is controlled by a duty cycling window. The transmitter core enables OOK data transmission with a ∼3.1 pJ/pulse energy budget, comprising master and slave PLL and antenna buffer contributions. The paper introduces the TX core architecture, details the master PLL operation and presents simulation results obtained in a 130 nm RFCMOS technology prior to measurement verification.

Estimation of asynchronous circuit performances, such as speed, is one of the major issues that make that design style still less popular than it deserves to be. Evaluating the worst case delays in the paths of an asynchronous circuit using a simple logic simulator would be very useful in overcoming this problem. In this paper a method for timing analysis of the asynchronous non-sequential circuits using a VHDL simulator is presented. With an appropriate extension of the standard logic simulation process, all worst case delays for all paths in a digital circuit with only one run of the simulation can be obtained. High levels of accuracy are achieved using different gate modelling and statistical analysis of the results. Due to the lack of asynchronous benchmark circuits, the method is verified on a set of asynchronous circuit selected by the authors.

An ultra-low-power 12-bit 200MS/s two-step pipelined SAR ADC is presented. In the first-stage SAR ADC, a separate DAC is applied with very small unit capacitors which generate the comparator decision threshold, thereby minimizing the required switching power. The dynamic register, which stores the comparator output, directly controls the DAC switch, dramatically reducing the SAR decision delay time. Based on the employed asynchronous SAR logic, the metastable state detection and correction logic can be implemented using a very simple digital logic. The prototype ADC in a 28nm CMOS process achieves a maximum SNDR of 64.8dB, resulting in a FoM of 7.7fJ/conversion-step.

This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.

Regular model checking is a form of symbolic model checking technique for systems whose states can be represented as finite words over a finite alphabet, where regular sets are used as symbolic representation. A major problem in symbolic model checking of parameterized and infinite-state systems is that fixpoint computations to generate the set of reachable states or the set of reachable loops do not terminate in general. Therefore, acceleration techniques have been developed, which calculate the effect of arbitrarily long sequences of transitions generated by some action. We present a systematic method for using acceleration in regular model checking, for the case where each transition changes at most one position in the word; this includes many parameterized algorithms and algorithms on data structures. The method extracts a maximal (in a certain sense) set of actions from a transition relation. These actions, and systematically obtained compositions of them, are accelerated to speed up a fixpoint computation. The extraction can be done on any representation of the transition relation, e.g., as a union of actions or as a single monolithic transducer. Using this approach, we are for the first time able to verify completely automatically both safety and absence of starvation properties for a collection of parameterized synchronization protocols from the literature; for some protocols, we obtain significant improvements in verification time. The results show that symbolic state-space exploration, without using abstractions, is a viable alternative for verification of parameterized systems with a linear topology.KeywordsModel CheckTransition RelationReachable StateLiveness PropertySymbolic Model CheckThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

Comparative research on cultural production and consumption

Since asynchronous circuits do not use clocks and perform operations based on causality relation between signal transitions, it is regarded that higher speed implementation and lower power consumption implementation than synchronous circuits are possible. In the design verification, however, since the number of states increases essentially more than in synchronous circuits, the computational time required in the verification increases. Accordingly, this paper proposes realization of verification based on trace theory by using ZBDD operations. Moreover, we will show that the higher speed implementation is possible by using Petri nets with inhibitor arcs, reducing the ZBDD variables by performing the composition of modules beforehand, and using special ZBDD operations for Petri nets. Finally, we will package the proposed scheme and carry out verification of several asynchronous circuits. © 2001 Scripta Technica, Syst Comp Jpn, 32(2): 43–54, 2001

An extension of trace theory is described that allows for the verification of asynchronous circuits that are not speed-independent, but instead rely on assumptions about the delays of their components for correct operation. The theory has been implemented in an automatic verifier that checks whether a circuit satisfies a given formal specification in time linear in the number of states of both the specification and the circuit. The ability of the verifier to model timing assumptions greatly expands the class of circuits that can be automatically verified, making the verifier a more useful tool in the design of asynchronous circuits. The verifier is demonstrated on a self-timed queue element. >