Framework of timed trace theoretic verification revisited

A combined delay model to manipulate the variance of the delay time of logic elements and a timing verification method based on the theory of regular expressions are presented. Emphasis is placed on the hazard detection problem and the verification of asynchronous circuits. The effectiveness of the method with medium sized circuits including about 100 elements is shown.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

We introduce a framework for the formal specification and verification of\nquantum circuits based on the Feynman path integral. Our formalism, built\naround exponential sums of polynomial functions, provides a structured and\nnatural way of specifying quantum operations, particularly for quantum\nimplementations of classical functions. Verification of circuits over all\nlevels of the Clifford hierarchy with respect to either a specification or\nreference circuit is enabled by a novel rewrite system for exponential sums\nwith free variables. Our algorithm is further shown to give a polynomial-time\ndecision procedure for checking the equivalence of Clifford group circuits. We\nevaluate our methods by performing automated verification of optimized\nClifford+T circuits with up to 100 qubits and thousands of T gates, as well as\nthe functional verification of quantum algorithms using hundreds of qubits. Our\nexperiments culminate in the automated verification of the Hidden Shift\nalgorithm for a class of Boolean functions in a fraction of the time it has\ntaken recent algorithms to simulate.\n

The self-timed (or asynchronous) approach to circuit design has demonstrated benefits in a number of different areas for its low energy consumption, high operating speed, composability, and modularity. Nonetheless, the asynchronous paradigm exposes challenges that are not found in the synchronous (or clock-driven) paradigm. For the verification task, a challenge emerges from the large number of potential operational interleavings exhibited in the asynchronous paradigm. Simply exploring all interleavings is, in general, intractable because the number of interleavings can grow exponentially. This dissertation focuses on developing scalable methods that are capable of reasoning effectively about the interleaving problem exhibited in self-timed systems. We specify and verify finite-state-machine representations of self-timed circuit designs using the DE system, a formal hardware description language defined using the ACL2 theorem-proving system. We apply a link-joint paradigm to model self-timed circuits as networks of channels that communicate with each other locally via handshake protocols. This link-joint model has been shown to be a universal model for various self-timed circuit families. In addition, this model has a clean formalization in the ACL2 logic and provides a protocol level that abstracts away timing constraints at the circuit level. Unlike many efforts for validating timing and communication properties of self-timed systems, we are interested in verifying functional properties. Specifically, we verify the functional correctness of self-timed systems in terms of relationships between their input and output sequences. To mitigate the consideration of all interleavings simultaneously, we address the verification problem hierarchically and avoid exploring the internal structures of verified submodules as well as their operational interleavings. The input-output relationship of a verified submodule is determined based on the communication signals at the submodule's input and output ports, while abstracting away all execution paths internal to that submodule.

Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits

An algebraic methodology based on Characteristic Functions (CFs) and allowing to compare switch-level circuits with higher-level specifications is presented.

With the rapid growth in the size and complexity of digital circuits, the possibility of bug occurrence has significantly increased. In order to avoid the enormous financial loss due to the production of buggy circuits, using scalable formal verification methods is essential. The scalability of a verification method for a specific design is proven by showing that the method has polynomial space and time complexities. Unfortunately, not all verification methods have a polynomial complexity, particularly when it comes to the verification of large and complex designs. In this paper, we propose a divide-and-conquer strategy for Polynomial Formal Verification (PFV) of complex circuits. Instead of using a monolithic proof engine to verify the entire design, we break the verification task down into several problems, which can be solved in polynomial space and time using a hybrid proof engine. As a case study, we investigate the PFV of the ALU in a RISC-V processor using our divide-and-conquer strategy.

We describe a methodology for analyzing timed systems symbolically. Given a formula representing a set of timed states, we describe howto determine a new formula that represents the set of states reachable by taking a discrete transition or by advancing time. The symbolic representations are given as formulae expressed in a simple first-order logic over constraints of the form x-y ? d which can be combined with Boolean operators and existentially quantified. The main contribution is a way of advancing time symbolically essentially by quantifying out a special variable z which is used to represent the current zero point in time. We describe how to model asynchronous circuits using timed guarded commands and provide examples that demonstrate the potential of the symbolic analysis.

New developments in the theory of Gröbner bases and applications to formal verification

Speed-independent circuits offer a potential solution to the timing problems of VLSI. In this book David Dill develops and implements a theory for practical automatic verification of these control circuits. He describes a formal model of circuit operation, defines the proper relationship between an implementation and its specification, and constructs a computer program that can check this relationship. Asynchronous or speed-independent circuit design has gained renewed interest in the VLSI community because of the possibilities it provides for dealing with problems that arise with the increasing complexity of VLSI circuits. Speed-independent circuits offer a way around such phenomena as clock skew, which can be a serious obstacle in the design of large systems. They can expedite circuit design by reducing design time and simplifying the overall process. A major challenge to the successful utilization of speed-independent circuits is correctness. The verification method described here insures that a design is correct and because it can be automated it is a significant advantage over manual verification. Dill proposes two distinct theories - prefix-closed trace structures, which can model and specify safety properties, and complete trace structures, which can also deal with liveness and fairness properties. Trace Theory for Automatic Hierarchical Verification of Speed Independent Circuits is a 1988 ACM Distinguished Dissertation

Ensuring the functional correctness of a digital system is achievable through formal verification. Despite the increased complexity of modern systems, formal verification still needs to be done in a reasonable time. Hence, Polynomial Formal Verification (PFV) techniques are being explored, as they provide guaranteed polynomial upper bounds on the time and space required for the verification process. Recently, it was shown that circuits characterized by a constant cutwidth can be verified in linear time using Answer Set Programming (ASP). However, these results are limited to combinational circuits, whereas most designs used in digital systems are sequential. In this paper, we introduce Linear Formal Verification (LFV) as a subclass of PFV for sequential circuits with constant cutwidth, which are verifiable in linear time and space using ASP. We achieve this by proposing a new data structure called Weighted And-Inverter Graph (W-AIG). Unlike existing formal verification methods, we prove that our approach can verify any sequential circuit with a constant cutwidth in linear time and space. Finally, we implement our approach and experimentally show that a variety of sequential circuits, such as pipelined adders, serial adders, and shift registers, can be verified in linear time and space, while ring counters can be verified in polynomial time and space, confirming our theoretical findings.

In this paper, we extend the verification method based on the failure semantics of process algebra and the resulting trace theory by Dill et al. for bounded delay asynchronous circuits. We define a timed conformance relation between trace structures which allows to express both safety and responsiveness properties. In our approach, bounded delay circuits as well as their real-time properties are modelled by time Petri nets. We give an explicit state-exploration algorithm to determine whether an implementation conforms to a specification. Since for IO-conflict free specifications the conformance relation is transitive, this algorithm can be used for hierarchical verification of large asynchronous circuits. We describe the implementation of our method and give some experimental results which demonstrate its efficiency.KeywordsTrace TheoryTime Petri NetsFailure AnalysisConformance CheckingState Space ExplorationAsynchronous CircuitsHardware VerificationDelay AnalysisReal Time SystemsComputer Aided Verification

Sequential Galois field (F 2k ) arithmetic circuits take k-bit inputs and produce a k-bit result, after k-clock cycles of operation. Formal verification of sequential arithmetic circuits with large datapath size is beyond the capabilities of contemporary verification techniques. To address this problem, this paper describes a verification method based on algebraic geometry that: i) implicitly unrolls the sequential arithmetic circuit over multiple (k) clock-cycles; and ii) represents the function computed by the state-registers of the circuit, canonically, as a multi-variate word-level polynomial over F 2k . Our approach employs the Grobner basis theory over a specific elimination ideal. Moreover, an efficient implementation is described to identify the k-cycle computation performed by the circuit at word-level. We can verify up to 100-bit sequential Galois field multipliers, whereas conventional techniques fail beyond 23-bit circuits.

Late detection of errors in hardware designs usually results in great costs. On the other hand, the growing advances on this field has let the complexity level to increase extensively. The problem is that the typical Hardware Description Languages (HDL) like VHDL and Verilog are made for synthesis and simulation only. But, the simulation technique could be deficient in complex designs such as the cryptographic circuits. Formal verification has became an important technique towards establishing the correctness of hardware designs. This paper presents a formal verification approach for the cryprographic circuits. It consists on using the functional language Haskell to formally describe both the behavioral and the structural descriptions. In addition, it relies on the use of the hierarchy and modularity techniques in order to reduce the complexity of the designs; and hence simplify the verification task. To show the potential features of the proposed approach, it is applied to the Data Encryption Standard (DES) circuit and its formal specification is presented.

One of the important issues in the asynchronous sequential circuit is to verify that the state transitions as stated in the specification occur even if there is a delay variation in the element. When the exiting timing verification method is applied to this problem, however, the transient and other states must be examined, which requires an exponentially long time in the verification. This paper presents a formal procedure based on the circuit structure and the relation between the specification and the circuit, where the state transition to induce the transition in the specification is determined and the state transition to be verified in detail is restricted without generating the transient and other states.First, the time‐invariant input values and state variable values are considered, and a sufficient condition is given for the above restriction. The sufficient condition ensures that the state transition occurs as is stated in the specification, independently of the element delay. A decision procedure for the sufficient condition is presented, and the time complexity is examined. It is shown that the proposed method is useful in reducing the verification time compared to the existing verification method. The sufficient condition is applied to sample circuits, and it is shown that the detailed verification can be omitted by the factor of 16/17 for the ring arbiter, and 20,24 for the D flip‐flop. Thus, it is expected that the time for the verification can be reduced greatly by the proposed method.

The increase in complexity of superconducting single flux quantum circuits enabled by the IARPA Cryogenic Computing Complexity project has highlighted the need for hardware description language (HDL) models that allow fast and reliable simulation and verification of such circuits. The design of new cell libraries for successive nodes of fabrication processes also exposed the cost of building new HDL models for each cell library. We expand an automatic HDL extraction method presented earlier to provide a fully automated tool for timing model extraction from an arbitrary cell the functionality of which does not need to be known. We describe in detail how models for the Verilog HDLs are constructed to allow timing verification and to implement delays as functions of bias, process tolerances, thermal noise, and load. Modeling of wire length delays is discussed, and results presented for complex circuits synthesized with new place-and-route algorithms.