Using unfoldings to avoid the state explosion problem in the verification of asynchronous circuits

A combined delay model to manipulate the variance of the delay time of logic elements and a timing verification method based on the theory of regular expressions are presented. Emphasis is placed on the hazard detection problem and the verification of asynchronous circuits. The effectiveness of the method with medium sized circuits including about 100 elements is shown.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The self-timed (or asynchronous) approach to circuit design has demonstrated benefits in a number of different areas for its low energy consumption, high operating speed, composability, and modularity. Nonetheless, the asynchronous paradigm exposes challenges that are not found in the synchronous (or clock-driven) paradigm. For the verification task, a challenge emerges from the large number of potential operational interleavings exhibited in the asynchronous paradigm. Simply exploring all interleavings is, in general, intractable because the number of interleavings can grow exponentially. This dissertation focuses on developing scalable methods that are capable of reasoning effectively about the interleaving problem exhibited in self-timed systems. We specify and verify finite-state-machine representations of self-timed circuit designs using the DE system, a formal hardware description language defined using the ACL2 theorem-proving system. We apply a link-joint paradigm to model self-timed circuits as networks of channels that communicate with each other locally via handshake protocols. This link-joint model has been shown to be a universal model for various self-timed circuit families. In addition, this model has a clean formalization in the ACL2 logic and provides a protocol level that abstracts away timing constraints at the circuit level. Unlike many efforts for validating timing and communication properties of self-timed systems, we are interested in verifying functional properties. Specifically, we verify the functional correctness of self-timed systems in terms of relationships between their input and output sequences. To mitigate the consideration of all interleavings simultaneously, we address the verification problem hierarchically and avoid exploring the internal structures of verified submodules as well as their operational interleavings. The input-output relationship of a verified submodule is determined based on the communication signals at the submodule's input and output ports, while abstracting away all execution paths internal to that submodule.

An algebraic methodology based on Characteristic Functions (CFs) and allowing to compare switch-level circuits with higher-level specifications is presented.

We describe a methodology for analyzing timed systems symbolically. Given a formula representing a set of timed states, we describe howto determine a new formula that represents the set of states reachable by taking a discrete transition or by advancing time. The symbolic representations are given as formulae expressed in a simple first-order logic over constraints of the form x-y ? d which can be combined with Boolean operators and existentially quantified. The main contribution is a way of advancing time symbolically essentially by quantifying out a special variable z which is used to represent the current zero point in time. We describe how to model asynchronous circuits using timed guarded commands and provide examples that demonstrate the potential of the symbolic analysis.

Since asynchronous circuits do not use clocks and perform operations based on causality relation between signal transitions, it is regarded that higher speed implementation and lower power consumption implementation than synchronous circuits are possible. In the design verification, however, since the number of states increases essentially more than in synchronous circuits, the computational time required in the verification increases. Accordingly, this paper proposes realization of verification based on trace theory by using ZBDD operations. Moreover, we will show that the higher speed implementation is possible by using Petri nets with inhibitor arcs, reducing the ZBDD variables by performing the composition of modules beforehand, and using special ZBDD operations for Petri nets. Finally, we will package the proposed scheme and carry out verification of several asynchronous circuits. © 2001 Scripta Technica, Syst Comp Jpn, 32(2): 43–54, 2001

This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or failures is developed. The concept of the semimirror is introduced to allow conformance checking thus supporting hierarchical verification of timed circuits and systems. Finally, we relate our framework to those previously proposed for timing verification.

An extension of trace theory is described that allows for the verification of asynchronous circuits that are not speed-independent, but instead rely on assumptions about the delays of their components for correct operation. The theory has been implemented in an automatic verifier that checks whether a circuit satisfies a given formal specification in time linear in the number of states of both the specification and the circuit. The ability of the verifier to model timing assumptions greatly expands the class of circuits that can be automatically verified, making the verifier a more useful tool in the design of asynchronous circuits. The verifier is demonstrated on a self-timed queue element. >

In this paper, we extend the verification method based on the failure semantics of process algebra and the resulting trace theory by Dill et al. for bounded delay asynchronous circuits. We define a timed conformance relation between trace structures which allows to express both safety and responsiveness properties. In our approach, bounded delay circuits as well as their real-time properties are modelled by time Petri nets. We give an explicit state-exploration algorithm to determine whether an implementation conforms to a specification. Since for IO-conflict free specifications the conformance relation is transitive, this algorithm can be used for hierarchical verification of large asynchronous circuits. We describe the implementation of our method and give some experimental results which demonstrate its efficiency.KeywordsTrace TheoryTime Petri NetsFailure AnalysisConformance CheckingState Space ExplorationAsynchronous CircuitsHardware VerificationDelay AnalysisReal Time SystemsComputer Aided Verification

Control theories for discrete event systems modeled as finite state machines have been well developed over the years in addressing various fundamental control issues. However, modeling in finite state machines has long suffered the potential problem of state explosion that renders it unsuitable for many practical applications. In this paper, we propose an approach that appends finite sets of parameters to finite state machines in modeling discrete event systems. We show with an example that many discrete event applications can then be represented efficiently in this approach and the state explosion problem can then been mitigated.

On the semantics of communicating hardware processes and their translation into LOTOS for the verification of asynchronous circuits with CADP

It is demonstrated that the binary inertial delay model can lead to false positive results when used in the verification of speed-dependent asynchronous circuits. A delay model called the binary chaos delay model solves this problem in many cases. The two timing models are compared by using them in the verification of a FIFO controller circuit. The models can be viewed as two extremes of a more general, parameterized model. >

This paper describes a reduction technique which is very useful against the state explosion problem which occurs when model checking many distributed systems. Timestamps are often used to keep track of the relative order of events. They are usually implemented with very large counters and therefore they generate state explosion. The aim of this paper is to present a very efficient reduction of the state space generated by a model checker when using timestamps. The basic idea is to map the timestamps values to the smallest possible range. This is done dynamically and on-the-fly by adding to the model checker a call to a reduction function after each newly generated state. Our reduction works for model checkers using explicit state enumeration and does not require any change in the model. Our method has been applied to an industrial example and the reduction obtained was spectacular.

The testing of Ajax (Asynchronous JavaScript and XML) web applications poses novel challenges for testers because Ajax constructs dynamic web applications by using Asynchronous communication and run time Document Object Model (DOM) manipulation. Ajax involves extreme dynamism, which induces novel kind of issues like state explosion, triggering state changes and unreachable states etc. that require more demanding web-testing methods. Model based testing is amongst the effective approaches to detect faults in web applications. However, the state model generated for an Ajax application can be enormous and may be hit by state explosion problem for large number of user action based changes and for immense dynamism. Recent research has not addressed this issue comprehensively because existing techniques either apply partial reduction or compromise the effectiveness of testing. This research uses soft computing based Fuzzy C Means (FCM) clustering algorithm to generate state machine model of an Ajax web application. The focus is on devising a framework to avoid the state explosion problem. The framework prioritizes the requirements and use cases based on requirements weightage, stakeholder weightage and user session based use case frequency. FCM uses this data to reduce the state space by identifying the most pivotal usage areas. The resultant DOM mutations for only these usage areas are considered to induce the finite state machine thus avoiding the state explosion. Experimental results show that the framework controls the size of generated state machine without compromising the effectiveness of testing.

Static analysis of concurrent programs has been hindered by the well-known state explosion problem. Although many different techniques have been proposed to combat this state explosion, there is little empirical data comparing the performance of the methods. This information is essential for assessing the practical value of a technique and for choosing the best method for a particular problem. In this paper, we carry out an evaluation of three techniques for combating the state explosion problem in deadlock detection: reachability searching with a partial-order state-space reduction, symbolic model checking and inequality-necessary conditions. We justify the method used for the comparison, and carefully analyze several sources of potential bias. The results of our evaluation provide valuable data on the kinds of programs to which each technique might best be applied. Furthermore, we believe that the methodological issues we discuss are of general significance in comparison of analysis techniques.

A heuristic transition executability analysis method for generating EFSM-specified protocol test sequences