A simple derivation of the Berlekamp- Massey algorithm and some applications (Corresp.)

Linear feedback shift registers and the minimal realization problem

The Berlekamp–Massey algorithm finds the shortest linear feedback shift register for a binary input sequence. A wide range of applications like cryptography and digital signal processing use this algorithm. This research proposes novel parallel mechanisms offered by heterogeneous CPU and GPU hardwares in order to achieve the best possible performance for BMA. The proposed bitwise implementation of the BMA algorithm is almost 35 times faster than state of the art implementations. This further improvement is achieved by using SIMD instructions which provides data level parallelism. This new approach can be 4.6 and 35 times faster than a bitwise CPU and state of the art implementations, respectively. In order to achieve the highest possible speedup over a multi-core structure, a multi-threading implementation is introduced in this research. By leveraging on OpenMP we were able to obtain a speedup of 10 times over 12 cores server. The GPU device with thousands of processing cores can bring great speedup over the best CPU implementation. Two other parallel mechanisms offered by GPU are concurrent kernel execution and streaming. They achieve 14.5 and 2.2 times of speedup compared to CPU serial and typical CUDA implementations, respectively. Also, the performance of the openMP code with SIMD instructions is compared with GPU stream implementation. The effectiveness of the proposed method is evaluated in a real world error correction application and it achieves 6.8 times of speedup.

This paper presents an efficient algorithm for encoding and decoding Shortened Reed-Solomon (SRS) codes based on evaluation. The encoding and syndrome computations are performed using polynomial evaluation and the decoding is performed using a recursive extension of the original algorithm. The proposed decoding algorithm initially calculates the error locator polynomial by using the Berlekamp Massey (BM) algorithm and with the recursive computation of discrepancies, it decodes directly the message polynomial. Compared to the traditional decoding algorithm using BM algorithm, Chien search and Forney formula, the proposed algorithm results in area savings for hardware implementations due to hardware re-use and the reduced number of stages. Also, the savings in memory for the software implementation makes it suitable for memory constrained applications such as Wireless Sensor Networks (WSN) applications. For the hardware implementations, the number of clock cycles required are lower for the proposed scheme, which results in time savings. Also, software implementation results of RS (32, 24) for resource constrained WSN application on ATMEL Atmega 128 microcontroller show that the proposed encoder and decoder is only about 52% and 72% of the memory footprint of a traditional encoder and decoder respectively.

A generalization of the Berlekamp-Massey algorithm is presented for synthesizing minimum length linear feedback shift registers for generating prescribed multiple sequences. A more general problem is first considered, that of finding the smallest initial set of linearly dependent columns in a matrix over an arbitrary field, which includes the multisequence problem as a special case. A simple iterative algorithm, the fundamental iterative algorithm (FIA), is presented for solving this problem. The generalized algorithm is then derived through a refinement of the FIA. Application of this generalized algorithm to decoding cyclic codes up to the Hartmann-Tzeng (HT) bound and Roos bound making use of multiple syndrome sequences is considered. Conditions for guaranteeing that the connection polynomial of the shortest linear feedback shift register obtained by the algorithm will be the error-locator polynomial are determined with respect to decoding up to the HT bound and special cases of the Roos bound.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

As the technology moves into the nano-realm, traditional single-error-correcting, double-error-detecting (SEC-DED) codes are no longer sufficient for protecting memories against transient errors due to the increased multi-bit error rate. The well known double-error-correcting BCH codes and the classical decoding method for BCH codes based on Berlekamp-Massey algorithm and Chien search cannot be directly adopted to replace SEC-DED codes because of their much larger decoding latency. In this paper, we propose the hierarchical double-error-correcting (HDEC) code. The construction methods and the decoder architecture for the codes are described. The presented error correcting algorithm takes only 1 clock cycle to finish if no error or a single-bit error occurs. When there are multi-bit errors, the decoding latency is O(log2m) clock cycles for codes defined over GF(2m). This is much smaller than the latency for decoding BCH codes using Berlekamp Massey algorithm and Chien search, which is O(k) clock cycles -- k is the number of information bits for the code and m ~ O(log2k). Synthesis results show that the proposed (79, 64) HDEC code requires only 80% of the area and consumes < 70% of the power compared to the classical (78, 64) BCH code. For a large bit distortion rate (10−3 ~ 10−2), the average decoding latency for the (79, 64) HDEC code is only 36% ~ 60% of the latency for decoding the (78, 64) BCH code.

Algebraic feedback shift registers (AFSRs) [] are pseudo-random sequence generators that generalize linear feedback shift registers (LFSRs) and feedback with carry shift registers (FCSRs). With a general setting, AFSRs can result in sequences over an arbitrary finite field. It is well known that the sequences generated by LFSRs can be synthesized by either the Berlekamp-Massey algorithm or the extended Euclidean algorithm. There are three approaches to solving the synthesis problem for FCSRs, one based on the Euclidean algorithm [], one based on the theory of approximation lattices [] and Xu’s algorithm which is also used for some AFSRs []. Xu’s algorithm, an analog of the Berlekamp-Massey algorithm, was proposed by Xu and Klapper to solve the AFSR synthesis problem. In this paper we describe an approximation algorithm that solves the AFSR synthesis problem based on low-dimensional lattice basis reduction []. It works for AFSRs over quadratic integer rings \(\mathbb {Z}[\sqrt{D}]\) with quadratic time complexity. Given the first \(2\varphi _\pi (\mathbf {a})+c\) elements of a sequence \(\mathbf {a}\), it finds the smallest AFSR that generates \(\mathbf {a}\), where \(\varphi _\pi (\mathbf {a})\) is the \(\pi \)-adic complexity of \(\mathbf {a}\) and \(c\) is a constant.

Safety-critical technology rests on optimised and effective testing techniques for every embedded system involved in the equipment. Pattern generator (PG) such as linear feedback shift register (LFSR) is used for fault detection and useful for reliability and online test. This study presents an analysis of the LFSR, using a known automatic test PG (ATPG) test set. Two techniques are undertaken to target difficult-to-detect faults with their respective trade-off analysis. This is achieved using Berlekamp-Massey (BM) algorithm with optimisations to reduce area overhead. The first technique (concatenated) combines all test sets generating a single polynomial that covers complete ATPG set (baseline-C). Improvements are found in Algorithm 1 reducing polynomial size through Xs assignment. The second technique uses non-concatenated test sets and provides a group of LFSRs using BM without including any optimisation (baseline-N). This algorithm is further optimised by selecting full mapping and independent polynomial expressions. Results are generated using 32 benchmarks and 65 nm technology. The concatenated technique provides reductions on area overhead for 90.6% cases with a best case of 57 and 39% means. The remaining 9.4% of cases, non-concatenated technique provides the best reduction of 37 with 1.4% means, whilst achieving 100% test mapping in both cases.

In 1969, J. Massey published a now-famous paper showing, among other things, that an iterative algorithm introduced by Berlekamp for decoding BCH codes also solved the problem of finding a shortest-length feedback shift register circuit for generating a given finite sequence of digits. This nice physical interpretation opened the door to connections with many other problems, including the minimal partial realization problems of linear system theory, Pade approximations and continued fractions, the fast algorithms of Levinson and Schur for Toeplitz matrices, inverse scattering, VLSI implementations, etc. This paper is an informal account of some of the different contexts in which the Berlekamp-Massey algorithm have been encountered in the work of the author and his students.

An algorithm for shifted continued fraction expansions in parallel linear time

The Berlekamp—Massey algorithm (further, the BMA) is interpreted as an algorithm for constructing Pade approximations to the Laurent series over an arbitrary field with singularity at infinity. It is shown that the BMA is an iterative procedure for constructing the sequence of polynomials orthogonal to the corresponding space of polynomials with respect to the inner product determined by the given series. The BMA is used to expand the exponential in continued fractions and calculate its Pade approximations.

The algebraic decoding of binary quadratic residue codes can be performed using the Peterson or the Berlekamp–Massey algorithm once certain unknown syndromes are determined. In this work, the technique of determining unknown syndromes is extended to the ternary case to decode the expurgated ternary quadratic residue code of length 37.

Transmission of image/video messages over communication networks is becoming a standard way of communication due to very efficient compression algorithms that reduce required channel capacity to an acceptable level. However, all compression standard techniques are strongly sensitivitive to channel disturbances and their application is suitable only for practically noiseless channels. In standard noisy channels, the effect of errors on a compressed data bit stream can be divided into two categories: systematic errors defined by the structure of data blocks, and random errors caused by amplitude changes of transmitted components. A systematic error can be detected at the receiver through control of the data stream structure and corrected by error concealment methods or by automatic repeat request (ARQ) procedures. Random errors, noise and burst-like errors, as well as impulse noise, should be controlled through channel coding. It is reasonable that an integrated source and channel coding methods should be preferred and should give better coding performance. In this paper, a new framework for an image/video coding approach has been presented in which the source and channel coding is integrated in a unique procedure. Image compression is performed in a standard way of the JPEG algorithm based on discrete cosine transform (DCT) and error control coding is based on the real/complex-number (N,M) BCH code using discrete Fourier transform (DFT) specified with zeros in the time domain, i.e. with roots in the frequency domain. Efficiency of the proposed method is tested on two examples, an one-dimensional real-valued time sequence coded by real-number (20,16) BCH code using DFT, and an example of an image coded by complex (10,8) BCH code using DFT with the correction ability of up to 8 impulses per transmitted 8×8 block. In addition, two decoding methods based on Berlekamp–Massey algorithm (BMA) and the minimum-norm algorithm (MNA) have also compared. Copyright © 1999 John Wiley & Sons, Ltd.

This paper presents a new scheme of Linear-Feedback Shift-Register (LFSR) reseeding technique based on Berlekamp-Massey Algorithm (BMA). It is proposed an LFSR-based TPG which its feedback polynomial is programmable by a BMA-synthesized LFSR that, in its turn, generates specific patterns to change the LFSR-based TPG's feedback polynomial. Using the proposed method, high fault coverage is achieved with a small number of test patterns. Experimental results have been shown the effectively of the proposed method.

A relationship between the Berlekamp-Massey and the Euclidean algorithms for linear feedback shift register synthesis is established. In fact, by refining a sequence of polynomials appearing in the Euclidean algorithm, the sequence of characteristic polynomials computed by the Berlekamp-Massey algorithm will be achieved.

Feedback shift registers with carry operation (FCSRs) are described, implemented, and analyzed with respect to memory requirements, initial loading, period, and distributional properties of their output sequences. Many parallels with the theory of linear feedback shift registers (LFSRs) are presented, including a synthesis algorithm (analogous to the Berlekamp-Massey algorithm for LFSRs) which, for any pseudorandom sequence, constructs the smallest FCSR which will generate the sequence. These techniques are used to attack the summation cipher. This analysis gives a unified approach to the study of pseudorandom sequences, arithmetic codes, combiners with memory, and the Marsaglia-Zaman random number generator. Possible variations on the FCSR architecture are indicated at the end.