A voltage-scalable 10-b pipelined ADC with current-mode amplifier

Improvement of diagnosis methodologies is a key factor for fast failure analysis and yield improvement. As bridging defects are a common defect type in CMOS circuits, diagnosing this class of defect becomes relevant for present and future technologies. Bridging defects cause two additional current components, the bridge and the downstream current. This work presents the effect of the downstream current on current signatures and its impact on the diagnosis of such defects. The authors demonstrate that the impact of downstream current is minimized at low power supply (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> ) values. Therefore, current measurements at low power supply voltages are proposed to enhance bridge diagnosis. Experimental evidence of this behaviour is presented for real devices. Furthermore, current signatures measured at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">VLV</sub> are used for the diagnosis of fifteen failing 0.18mum technology devices, which are demonstrated to contain a bridging defect.

As feature sizes of integrated circuits continue to shrink and demand for low power operation continues to increase, power supply voltages may eventually be reduced to the level where noise becomes significant compared with signals. This would cause digital logic circuits to exhibit non-deterministic behavior. In this paper, we study the stochastic behavior of simple digital circuits operating at low power supply voltages. We develop a method for modelling the stochastic behavior of circuits and apply the method to a CMOS inverter. We use numerical simulations of stochastic differential equations to obtain time- domain transient analysis of the CMOS inverter and magnitude statistics from multiple sample paths. Further, we derive the output distribution at steady state from first principles. We characterize the switching error and the information transmission based on the output steady state distribution. This study provides a detailed understanding of how noise affects the operation of the CMOS inverter at low power supply voltages. The method we develop here can also be extended to other circuits where stochastic sample paths and sample statistics are necessary to characterize the circuits. Traditional frequency domain noise analysis is not adequate to provide this information.

Bridging faults in CMOS circuits sometimes degrade the output voltage and time performance without altering the logic function. The traditional voltage testing models based on the normal power supply voltage do not accurately model this behavior. In this paper we develop a model of bridging faults that accounts for both the bridging resistance distribution and gate sensitization and propagation choices. This model shows that fault coverage increases at lower power supply voltages. It suggests that decreasing the power supply voltage is a promising technique to maximize the real fault coverage of voltage tests, thereby minimizing the number of relatively slow Iddq tests required to achieve high quality.

We have investigated circuit options to surpass the 1 V power-supply limitation predicted by traditional scaling guidelines. By modulating the body bias, we can dynamically adjust the threshold voltage to have different on- and off-state values. Several dynamic threshold voltage MOSFET (DTMOS) logic styles were analyzed for ultralow-power use-from 1.5 down to 0.5 V. Since ordinary pass-transistor logic degrades as the voltages are reduced, we investigated the effects that a dynamic threshold has on various styles of pass-transistor logic. Three different pass-transistor restoration schemes were simulated with the various DTMOS techniques. Results indicate that controlling the body bias can provide a substantial speed increase and that such techniques are useful over a large range of supply voltages. Process complexity and other tradeoffs associated with DTMOS logic variations are also discussed.

This paper presents a single VDTA based Mixed Mode type Biquad filter. The proposed Transadmittance Mode (TAM) type Biquad filter configuration employed single voltage differencing transconductance amplifier (VDTA) as an active building block, three passive element namely one grounded resistor, one grounded capacitor and one floating capacitor. The proposed transadmittance Mode multifunction Biquad filter configuration is presenting transadmittance mode type four basic standard filter functions low pass, high pass, band pass, band reject or band stop or band eliminate filter responses. These four type filter responses are realizing simultaneously with the selection of single input voltage signal. The proposed Transadmittance Mode multifunction Biquad filter configuration has more advantageous features such as low active and passive sensitivities, low power supply voltage, low power consumption, low quality factor, very low power consumption, more electronic tunability, higher linearity and required small area of the chip. The performance of the proposed configuration has been verified through PSPICE simulation using 0.18μm CMOS Technology process parameters.

This paper presents two new circuit topologies of dc bus line series active snubber assisted soft switching PWM full-bridge dc-dc power converter acceptable for either utility ac 200 V-rms or ac 400 V-rms input voltage source. One of proposed power converters is composed of a typical voltage source full-bridge high frequency PWM inverter using dc bus line side series switching devices with the aid of a parallel capacitive lossless snubber. All the active power switches in the full-bridge arms and dc bus line can achieve ZCS turn-on and ZVS turn-off commutation operation and consequently the total turn-off switching losses can be significantly reduced. As a result, a high switching frequency for used IGBTs can be actually realized more than about 20 kHz. It is proved that the more the switching frequency of full-bridge inverter increases, the more soft switching PWM dc-dc power converter with a high frequency transformer link has remarkable advantages for its power conversion efficiency and power density as compared with the conventional hard switching PWM inverter type dc-dc converter. The effectiveness of this new converter topology is proved for low voltage and large current dc-dc power supplies as arc welding machine from a practical point of view

One of the major problems faced by the designer when operating CMOS static logic circuits at low power supply voltages (normalized to V/sub T/) is that the delay spread introduced by today's IC manufacturing variations can increase dramatically. In this paper we describe an approach for decreasing the delay spread and power spread in ICs based on adaptively servoing the circuits between static CMOS operation and QuadRail operation. An on-chip series-regulator employing a dummy delay path is used to generate the adaptive low swing power supply rails making this approach fully compatible with a standard CMOS IC design methodology. Simulation results are presented demonstrating that for a 16*16+36-bit multiplier-accumulator designed in 0.5 /spl mu/m CMOS process the proposed approach decreases the delay spread from 3.9/spl times/ to 2.3/spl times/ and the power spread from 3.6/spl times/ to 1.8/spl times/.

Test application at reduced power supply voltage (or VLV testing) is a cost-effective way to increase the defect coverage of a test set. Resistive short defects are a major contributor to this coverage increase. Using a probabilistic model of these defects, we quantify the coverage impact of VLV testing for different voltages. When considering the coverage increase, we differentiate between defects missed by the test set at nominal voltage and undetectable defects (flaws) detected by VLV testing. In our analysis, the performance degradation of the device caused by lower power supply voltage is accounted for. Furthermore, we describe a situation in which defects detected by conventional testing are missed by VLV testing and quantify the resulting coverage loss. We report the numbers on the increased defect coverage, flaw coverage, and coverage loss for ISCAS circuits.

Design and analysis of a low-swing driver scheme for long interconnects

Polysilicon emitter design for scaled BiCMOS circuits

The long-pulse power-supply system equipped for the 4 MW beam-power ion source is comprised of three units at ASIPP (Institute of Plasma Physics, Chinese Academy of Sciences): one for the neutral-beam test stand and two for the EAST neutral-beam injectors (NBI-1 and NBI-2, respectively). Each power supply system consists of two low voltage and high current DC power supplies for plasma generation of the ion source, and two high voltage and high current DC power supplies for the accelerator grid system. The operation range of the NB power supply is about 80 percent of the design value, which is the safe and stable operation range. At the neutral-beam test stand, a hydrogen ion beam with a beam pulse of 150 s, beam power of 1.5 MW and beam energy of 50 keV was achieved during the long-pulse testing experiments. The result shows that the power-supply system meets the requirements of the EAST-NBIs fully and lays a basis for achieving plasma heating.

In this paper a low-power current-mode RMS-to-DC converter is proposed. The proposed converter includes absolute value circuit, squarer/divider circuit, low-pass filter and square root circuit which employ CMOS transistors operating in weak inversion region. The RMS-to-DC converter has low power consumption (&lt;1μW), low supply voltage (0.9V), wide input range (from 50 nA to 500 nA), low relative error (&lt;3 %), and low circuit complexity. Comparing the proposed circuit with two other current-mode circuits shows that the former outperforms the latters in terms of power dissipation, supply voltage, and complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

A portable, low power, digital spectroscopy for CdZnTe (CZT) detector is designed and described in this paper. Its readout electronics is implemented with waveform sampling, Flash-based FPGA (Field Programmable Gate Array) and USB (universal serial bus) technique. The CZT detector, with an effective thickness of 3mm and a diameter of 5mm, is mounted on the same PCB board with high voltage supply module and low noise preamplifier. Current signal from CZT detector is integrated by a charge sensitive amplifier and then shaped by a CR-RC 3 shaper. The shaped signal is sampled by a 12-bit ADC and then processed by an IGLOO Flash-based low power FPGA in a digital module. A USB interface is adopted both for low voltage and high voltage power supply, and communicating with a host computer, which results in a portable solution with maximum power consumption of about 450mW. In the host computer, a graphic user interface (GUI) software is developed based on Labwindows/CVI, for real-timely displaying the energy spectrum or waveform of shaping signal. Test results showed that the dynamic range of the spectroscopy can reach 240fC (equivalent to about 7 MeV energy deposition in CZT detector) and the intrinsic noise (in RMS) for the electronics is less than 0.3fC (equivalent to about 8.7 keV).

We propose a simple current reference circuit with low power supply voltage dependence and low temperature coefficient by combining output currents of conventional current mirror and Nagata current source. Detailed analysis and design procedure are presented. Preliminary test chip measurement results are also represented. Temperature dependence of the output current was compensated by synthesizing required temperature coefficient of a resistor from different types of on chip resistors. The output current indicated +200 ppm/deg temperature coefficient by circuit simulation, and is an order of improvement over without temperature compensation case. The proposed current reference circuit does not have positive feedback loop, thus, it is free from start-up problem unlike beta-multiplier. Design example indicated far better performance against power supply voltage change and temperature change than simple current mirror.

A vision chip based on pulse frequency modulation (PFM) is proposed as a retinal prosthesis device for use in subretinal implantation. A pixel circuit of PFM has been fabricated using standard CMOS technology. A dynamic range of 40 dB is demonstrated at a low power supply voltage of 1 V. It is found that the competition between the charge current to the photodiode and the photocurrent affects the output pulse characteristics under the conditionds of low power supply voltage and strong light illumination. For in vitro and in vivo experiments, two methods of improving the PFM circuits are considered. One is controlling the pulse frequency. By adding one transistor to the PFM circuit, the output pulse frequency can be experimentally controlled by a factor of two. The other is using a biphasic output, which is required to keep a charge balance in a living body. By introducing differential circuits, the biphasic output has been confirmed by simulation.