An efficient small‐delay faults simulator based on critical path tracing

Introduction: Contact tracing has the potential to control outbreaks without the need for stringent physical distancing policies, e.g. civil lockdowns. Unlike forward contact tracing, backward contact tracing identifies the source of newly detected cases. This approach is particularly valuable when there is high individual-level variation in the number of secondary transmissions (overdispersion). Methods: By using a simple branching process model, we explored the potential of combining backward contact tracing with more conventional forward contact tracing for control of COVID-19. We estimated the typical size of clusters that can be reached by backward tracing and simulated the incremental effectiveness of combining backward tracing with conventional forward tracing. Results: Across ranges of parameter values consistent with dynamics of SARS-CoV-2, backward tracing is expected to identify a primary case generating 3-10 times more infections than average, typically increasing the proportion of subsequent cases averted by a factor of 2-3. The estimated number of cases averted by backward tracing became greater with a higher degree of overdispersion. Conclusion: Backward contact tracing can be an effective tool for outbreak control, especially in the presence of overdispersion as was observed with SARS-CoV-2.

A reliable method for delay fault diagnosis, based on critical path tracing from symbolic simulation of the fault-free circuit, is presented. It does not require timing evaluations and may be very accurate. The diagnosis method consists of simulation of the fault-free circuit with a six-valued logic algebra and a tracing of critical paths from primary outputs to primary inputs. The proposed method is an alternative to fault simulation. It requires no delay size based fault models and considers only the fault-free circuit. Consequently, this approach is faster, reliable, and requires less memory than conventional fault simulation. To improve the diagnosis accuracy, the concept of sensitive lines has been developed. Based on the method presented, a fast algorithm has been implemented in C++ on a SUN-SPARC workstation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The paper presents a concept of single event equivalence to be used in the sequential circuit fault simulator. The concept dynamically identifies the equivalent faults for a simulated pattern. It combines advantages of the fanout-free region, critical path tracing and the dominator concept, which were applicable only to combinational circuit fault simulation. The implemented fault simulator, SEESIM, based on the concept, demonstrated a performance superior to that of a state-of-the-art concurrent fault simulator, and comparable to that of parallel-pattern single-fault propagation simulators. It requires a minimal amount of memory and, because of its simplicity, can be easily extended to multilogic or higher level simulation.

Die cavity design of near flashless forging process using FEM-based backward simulation

Backward tracing simulation of precision forging process for blade based on 3D FEM

The authors discuss possibilities of delay fault diagnosis based on fault simulation. They detail the proposed approach based on critical path tracing. A path tracing process is presented with information provided by a logic simulation. Due to the limitations induced by such a simulation, a reliable approach is described based on a six-valued logic simulation. It requires no delay size based fault models and considers only the fault-free circuit. This method is an alternative to fault simulation based approaches and provides perfectly reliable results. It does not require timing evaluations and can be very accurate. >

Critical path tracing has been shown to be faster than traditional fault simulation methods, but it produces pessimistic results in some cases involving reconvergent fanout. It is shown that the pessimistic nature of critical path tracing in combinational circuits can lead to incorrect results that are not necessarily pessimistic in sequential circuits. A modification of the method for removing the approximation is proposed, and a critical path tracing algorithm for synchronous sequential circuits is presented. >

The integrated circuit (IC) design has been pushed to hardware description language (HDL) description and high-level synthesis (HLS) techniques. The IC testing is also going to the high-level one. For the high-level testing, like gate level one, it needs a circuit model at high level such that, The model is easy to be converted and extended from the HDL descriptions. The model should be unified for multiple usages such as fault simulation, test generation, testability measure, etc. For various algorithms, it is easy to perform forward and backward tracing on the model, and easy to define fault models. In this paper, we try to construct such model and apply it to the fault simulation first.

BackgroundThere are several situations in population biology research where simulating DNA sequences is useful. Simulation of biological populations under different evolutionary genetic models can be undertaken using backward or forward strategies. Backward simulations, also called coalescent-based simulations, are computationally efficient. The reason is that they are based on the history of lineages with surviving offspring in the current population. On the contrary, forward simulations are less efficient because the entire population is simulated from past to present. However, the coalescent framework imposes some limitations that forward simulation does not. Hence, there is an increasing interest in forward population genetic simulation and efficient new tools have been developed recently. Software tools that allow efficient simulation of large DNA fragments under complex evolutionary models will be very helpful when trying to better understand the trace left on the DNA by the different interacting evolutionary forces. Here I will introduce GenomePop, a forward simulation program that fulfills the above requirements. The use of the program is demonstrated by studying the impact of intracodon recombination on global and site-specific dN/dS estimation.ResultsI have developed algorithms and written software to efficiently simulate, forward in time, different Markovian nucleotide or codon models of DNA mutation. Such models can be combined with recombination, at inter and intra codon levels, fitness-based selection and complex demographic scenarios.ConclusionGenomePop has many interesting characteristics for simulating SNPs or DNA sequences under complex evolutionary and demographic models. These features make it unique with respect to other simulation tools. Namely, the possibility of forward simulation under General Time Reversible (GTR) mutation or GTR×MG94 codon models with intra-codon recombination, arbitrary, user-defined, migration patterns, diploid or haploid models, constant or variable population sizes, etc. It also allows simulation of fitness-based selection under different distributions of mutational effects. Under the 2-allele model it allows the simulation of recombination hot-spots, the definition of different frequencies in different populations, etc. GenomePop can also manage large DNA fragments. In addition, it has a scaling option to save computation time when simulating large sequences and population sizes under complex demographic and evolutionary situations. These and many other features are detailed in its web page [1].

In this paper, we propose a method of diagnosing gate delay faults using delay fault simulation. In the method, suspected faults are deduced by fault simulation and backward path-tracing using diagnostic test-pairs with observed faulty responses. Also, by fault simulation using diagnostic test-pairs with fault-free responses, non-existent faults are deduced, and they are removed from the set of suspected faults. Finally, we present experimental results on the ISCAS'85 benchmark circuits. The experimental results show that by simple processes of backward path-tracing and fault simulation, this method achieves reasonable diagnostic resolutions in a short time.

An upper bound elemental technique approach to the process design of axisymmetric forging by forward and backward simulation

In this paper we propose a methodology which combines Forward and Backward Simulation in order to extend discrete-event simulation by the ability to calculate float times. In the case of Backward Simulation, the simulation starts at the virtual completion date of the construction project and runs backwards in time until the start date. To determine float times it is important that the task execution sequence is in the same order for forward and backward simulation. Consequently we present an extension to the simulation concept that controls the execution order of the tasks within the backward simulation. By combining the results of the forward and backward simulation, it is possible to determine float times for each task while taking into account resources. A comprehensive case study illustrates the application of this new approach. One result of this is the determination of detailed float times for each task using discrete-event simulation.

A systematic procedure for locating resistive bridges is presented. Critical path tracing is used to identify a set of suspect bridges whose presence could explain all of the observed faulty behavior of the circuit for the original test set. The set of suspects is then reduced by adaptively applying additional tests derived from the failing vector pairs in the original test set. Unlike other approaches, the approach presented here is not based on any bridge fault modeling and does not require any fault simulation.

A fault simulator for large synchronous sequential circuits is presented in this paper. There are four key ideas to the fault simulator. (1) It uses the critical path tracing method to screen out the single event faults that need not map into equivalent stem faults. (2) It uses the single fault propagation method to map the traced single event faults into equivalent stem faults. (3) All the multiple event faults are dynamically ordered for each test pattern such that the faults with the same faulty effects can be put into the same packet, so as to reduce the number of events created during simulation. (4) All the packets are propagated simultaneously; therefore, each gate is simulated only once for each test pattern, and while propagating packets, equivalent stem faults are also inserted into the packets and propagated as well. A memory sharing technique is used to reduce the memory overhead. Experimental results show that our fault simulator runs faster than PROOFS, HOPE, and improved HOPE (HOPE1.1) for large synchronous sequential benchmark circuits.

In the first part of the chapter, an introduction to the problem of logic level fault simulation is given together with the overview of existing fault simulation techniques. The remaining part of the chapter describes a new approach to fault simulation based on exact critical path tracing to conduct fault analysis in logic circuits. A circuit topology driven computational model is presented which allows not only to cope with complex structures of nested reconvergent fan-outs but also to carry out the fault reasoning for many test patterns concurrently. To achieve the speed-up of backtracing, the circuit is simulated on higher than traditional gate level. As components of the circuit network, fan-out free regions of maximum size are considered, and they are represented by structurally synthesized BDDs. The latter allow to reduce the number of internal variables in the computation model, and therefore to process the whole circuit faster than on the flat gate-level. The method is explained first, for the stuck-at fault model, and then generalized for an extended class of functional fault model covering the conditional stuck-at and transition faults. The method can be used for simulating permanent faults in combinational circuits, and transient or intermittent faults both in combinational and sequential circuits with the goal of selecting malicious faults for injecting into fault tolerant systems to evaluate their dependability. Experimental results are included to give an idea how efficiently the method works with different fault classes.