Delay-fault diagnosis based on critical path tracing from symbolic simulation

primary outputs to primary inputs. The proposed method is an alternative to fault simulation. It requires no delay size based fault modeh and considers only the fault-free circuit. consquently, this approach is faster, reliable and requires less memory than conventional fault simulation. The class offaultsknown as delayfauh investigatedin this paper. The Diagnosis process is autOdicallY implemented ajter the detection Of a fault in a circuit. Unfortunately, the existing methodologies for locating timing failures on digital circuits have shown certain deficiencies. A new and reliable method for &lay faulr 2, Detection of a Delay Fault diagnosis, based on the symbolic simulation of the fault-f?ee circuit, is presented.

The authors discuss possibilities of delay fault diagnosis based on fault simulation. They detail the proposed approach based on critical path tracing. A path tracing process is presented with information provided by a logic simulation. Due to the limitations induced by such a simulation, a reliable approach is described based on a six-valued logic simulation. It requires no delay size based fault models and considers only the fault-free circuit. This method is an alternative to fault simulation based approaches and provides perfectly reliable results. It does not require timing evaluations and can be very accurate. >

In this paper, we propose a timing-reasoning algorithm to improve the resolution of delay fault diagnosis. In contrast to previous approaches which identify candidates by utilizing only logic conditions, we propose a timing-simulation-based method to perform the candidate reasoning. Based on the circuit timing information, we identify invalid candidates which cannot maintain the consistency of failure behaviors. By eliminating those invalid candidates, the diagnosis resolution can be improved. We then analyze the problem of circuit timing uncertainty caused by the delay variation and the simulation model. We calculate a metric, named invalid-probability, for each candidate. Then we propose a candidate-ranking heuristic which is robust with respect to such sources of timing uncertainty. By ranking the candidates based on their invalid-probability, we can improve the candidate first-hit-rate of the traditional critical path tracing (CPT) technique. To demonstrate the efficiency of the proposed method, we have developed a timing diagnosis framework which can simulate the real diagnosis process to evaluate and compare different algorithms.

SummaryTesting for small‐delay defects (SDDs) has become an important component of integrated circuit testing. In this paper, an efficient small‐delay fault simulator, a hybrid method combining forward serial simulation and backward critical path tracing simulation for SDDs is proposed, which aims to determine the coverage of small‐delay defects for a given test set fast and accurately. In our proposed method, a unit delay model is employed, and reconvergent sensitization as well as hazard‐based detection is considered. Signal waveforms are expressed by bitmap data forms. In addition to providing an accurate result for fault simulation, the proposed simulator can well assist test generation. Experimental results demonstrate that the proposed simulator can further accelerate the simulation by one or two orders of magnitude compared with previous works. Copyright © 2014 John Wiley & Sons, Ltd.

Critical path tracing has been shown to be faster than traditional fault simulation methods, but it produces pessimistic results in some cases involving reconvergent fanout. It is shown that the pessimistic nature of critical path tracing in combinational circuits can lead to incorrect results that are not necessarily pessimistic in sequential circuits. A modification of the method for removing the approximation is proposed, and a critical path tracing algorithm for synchronous sequential circuits is presented. >

The paper presents a concept of single event equivalence to be used in the sequential circuit fault simulator. The concept dynamically identifies the equivalent faults for a simulated pattern. It combines advantages of the fanout-free region, critical path tracing and the dominator concept, which were applicable only to combinational circuit fault simulation. The implemented fault simulator, SEESIM, based on the concept, demonstrated a performance superior to that of a state-of-the-art concurrent fault simulator, and comparable to that of parallel-pattern single-fault propagation simulators. It requires a minimal amount of memory and, because of its simplicity, can be easily extended to multilogic or higher level simulation.

This paper discusses gate open-circuit fault detection and diagnosis method in SPWM modulated symmetric cascaded H-bridge multilevel inverter. First, an output voltage modelling under fault condition in cascaded H-bridge multilevel inverter is presented. Further, simulations of fault conditions have been carried out for the development of the fault detection and diagnosis method. Based on fault modelling and simulations, a fault detection and diagnosis method have been proposed based on the mean values of the bridge voltages as the diagnostic feature. Further, the proposed method has been validated experimentally on a 5-level symmetric sine pulse width modulated cascaded H-bridge multilevel inverter.

The goal of fault diagnosis is to identify the causes of device failures. Different techniques have been proposed for stuck-at fault diagnosis in combinational as well as sequential circuits. On the other side, diagnosis of delay faults has received attention for the first category of circuits, but not for synchronous sequential circuits. So, this paper concerns delay fault diagnosis for non-scan circuits. A preliminary version of the proposed method is first given. New concepts for allowing path tracing in the proposed diagnosis process (identification of self-masking) are also presented. As the method is based on path tracing through the sequential circuit, gate delay faults as well as path delay faults are considered and may be located in a faulty machine. Results of experiments on ISCAS-89 benchmark circuits are finally discussed.

A systematic procedure for locating resistive bridges is presented. Critical path tracing is used to identify a set of suspect bridges whose presence could explain all of the observed faulty behavior of the circuit for the original test set. The set of suspects is then reduced by adaptively applying additional tests derived from the failing vector pairs in the original test set. Unlike other approaches, the approach presented here is not based on any bridge fault modeling and does not require any fault simulation.

This paper presents a diagnosis methodology targeting most of the fault models used in practice today. This methodology is intended to be used to diagnose faulty behaviors in nanometric circuits for which the classical stuck-at fault model is far to cover all the realistic failures. The first phase of this methodology consists in the application of an Effect-Cause approach which relies on the two following main operations. The first one is based on critical path tracing (CPT) and consists in identifying lines in the Circuit Under Test (CUT) which can be the source of observed errors. The second one consists in allocating a set of possible fault models to each suspected line. In a second phase, we resort to a Cause-Effect approach applied on the set of suspects previously identified to prune the unlikely candidates and thus improve diagnosis resolution. The main advantage of this method is that it considers logical effects of the faults and does not need to handle each specific fault model explicitly during the diagnosis process. Experiments on ISCAS'89 and ITC'99 benchmark circuits show the efficiency of the proposed method in terms of diagnosis resolution.

Analog fault diagnosis using S-transform preprocessor and a QNN classifier

In this paper, we propose a method of diagnosing gate delay faults using delay fault simulation. In the method, suspected faults are deduced by fault simulation and backward path-tracing using diagnostic test-pairs with observed faulty responses. Also, by fault simulation using diagnostic test-pairs with fault-free responses, non-existent faults are deduced, and they are removed from the set of suspected faults. Finally, we present experimental results on the ISCAS'85 benchmark circuits. The experimental results show that by simple processes of backward path-tracing and fault simulation, this method achieves reasonable diagnostic resolutions in a short time.

Atomic digraphs are applied to fault description and simulation in combinational circuits. Using these graphs, it is possible to simulate both the correct circuit and the presence of any simple or multiple stuck-at fault. The proposed method permits the efficient generation of tests.

Abs t rac t A new class of fault simulation algorithms, that have recently been developed for gate-level fault simulation and shown to have several advantages over concurrent fault simulation, are adapted for switch-level fault simulation. High speed compiled switch-level simulation is used for circuit evaluation that approaches the speed of gate-level simulation. The fault simulation algorithms are single fault propagation, differential fault simulation, active fault simulation and parallel active fault simulation. Using these algorithms, minimum memory requirements and high simulation efficiency are achieved, both of which are essential to performing practical fault simulation at the switch-level due to the large number of switch-level faults.

Dissolved gas analysis is one of the most effective methods for diagnosing transformer faults. The traditional method for oil-immersed transformer fault diagnosis can only recognize several types of defects and has a low accuracy rate. In order to improve the classification effectiveness, a refined classification method for transformer fault diagnosis is proposed. It can detect more types of faults with a higher accuracy rate. The proposed method is based on the probability-output relevance vector machine, and a three-layer four-classifier model is constructed to analyse the different diagnostic results of different kinds of input data. In this model, a binomial tree is used to transfer the multi-classification problem to four binary classification problems; each classifier is a binary classifier used to distinguish the transformer type between two types of error. The proposed method is employed for analysis of 100 DGA samples consisting of characteristic gas content. The experimental result shows that this method has a high diagnostic rate and can diagnose 11 kinds of operation state.