An Improved VLSI Architecture of S-box for AES Encryption

This paper compares ASIC and FPGA implementations of two commonly used architectures for 2-dimensional discrete cosine transform (DCT), the parallel and folded architectures. The DCT has been designed for sizes 4x4, 8x8, and 16x16, and implemented on Silterra 180nm ASIC and Xilinx Kintex Ultrascale FPGA. The objective is to determine suitable low energy architectures to be used as their characteristics greatly differ in terms of cells usage, placement and routing methods on these platforms. The parallel and folded DCT architectures for all three sizes have been designed using Verilog HDL, including the basic serializer-deserializer input and output. Results show that for large size transform of 16x16, ASIC parallel architecture results in roughly 30% less energy compared to folded architecture. As for FPGAs, folded architecture results in roughly 34% less energy compared to parallel architecture. In terms of overall energy consumption between 180nm ASIC and Xilinx Ultrascale, ASIC implementation results in about 58% less energy compared to the FPGA.

<title>Abstract</title> This work presents an AI-enabled low-power UART (Universal Asynchronous Receiver Transmitter) architecture optimized for advanced automotive applications using a hybrid front-end and back-end design approach. The front-end design and functional verification are carried out in Vivado, while the back-end physical implementation and power optimization are performed using the Sky Water 130 nm PDK technology. The proposed design integrates artificial intelligence–based optimization strategies to enhance communication efficiency and minimize total power dissipation. Machine learning techniques, including reinforcement learning and regression-based prediction, are employed to analyse switching activity and workload behaviour, enabling real-time adaptive control of key operating parameters such as voltage, frequency, and clock gating. By incorporating dynamic voltage and frequency scaling (DVFS) and adaptive clock gating, the architecture achieves notable reductions in both dynamic and static power while maintaining high data integrity. The AI-assisted UART intelligently manages buffer utilization and module activation based on data traffic patterns, leading to superior energy efficiency and performance balance. Simulation and physical verification demonstrate significant improvements in power, latency, and area compared to conventional UART architectures. The proposed architecture provides a scalable, energy-efficient, and intelligent communication interface, ideally suited for next-generation automotive embedded and sensor systems requiring low power and high reliability.

Adders are plays a vital role in digital and vlsi systems. Arithmetic operations are an essential part of digital systems. During VLSI systems, the entire research is on lowering the scale of transistors for enforcing any other digital system. This proposed architecture implemented by different types of logic systems; each logic performs the different role in the hybrid system. The hybrid Full Adder cell with one bit is implemented in this structure. The proposed method is investigated using 22-nm CMOS hybrid full adder. The proposed architecture demonstrates substantial efficiency in power consumption and delay, based on simulation results. The simulation result expressed that the full adder circuit is used to modern high speed central processing unit in the data path architecture. This form of hybrid Full Adder, reduces the delay and increasing efficiency and mainly used in nano technology applications. The average power consumption of $1.1055 {\mu}\mathrm{W}$ with moderately low delay of 7.0415ps was found to be extremely low for 0.8-V supply at 22-nm technology. These kind of adder allocates significant improvements in power, high speed and area compared with previous full adder designs.

This work proposes a novel low power/area digital architecture for a Linear Program (LP) solver based on a recurrent (non-linear feedback) Neural Network (RNN), which is applied for spatial localization of sensors. Training data is not needed in our approach. We solve the primal and dual optimization problems for spatial localization with a single multi-functional data path which does not require matrix inversions. FPGA and ASIC implementations are presented which target a sensor (microrobot) localization problem in 2D using angle-of-arrival (AOA) measurements. The results show that the estimated locations (2D coordinates) are very close to the ground truth values in all tested scenarios. The proposed RNN has input and output layers, and a hidden layer with four neurons. FPGA implementation of the localizer in 180 nm process dissipates 180 mW of power at 1.5V and 31.25 MHz. When scaled to 128 neurons the performance is 13 Mop/sec/W for the same FPGA technology. The design has been also simulated in an ASIC 45 nm (PDK45 1V VDD) standard cell technology. With 128 neurons in the hidden layer the ASIC consumes 196.9 mW power at 516 MHz, which is equivalent to 677.165 Mop/sec/W.

This paper proposes a low-power implementation of the approximate logarithmic multiplier to improve the power consumption of convolutional neural networks for image classification, taking advantage of its intrinsic tolerance to error. The approximate logarithmic multiplier converts multiplications to additions by taking approximate logarithm and achieves significant improvement in power and area while having low worst-case error, which makes it suitable for neural network computation. Our proposed design shows a significant improvement in terms of power and area over the previous work that applied logarithmic multiplication to neural networks, reducing power up to 76.6% compared to exact fixed-point multiplication, while maintaining comparable prediction accuracy in convolutional neural networks for MNIST and CIFAR10 datasets.

The method how to design a safety device of railway station efficiently and scalable is proposed. The safety device for any configuration of railway station can be built from five basic blocks. These basic blocks are connected together with universal interface. Each block is based on a finite state machine. The finite state machines are Moore type. Each state machine is divided into three basic parts, where each part is designed as a self- checking circuit ensuring fault detection. Our methodology is intended for final implementation in FPGA and hence SEU faults occurring in the system is assumed.

I is common to study the history of a technology with a growth curve showing the annual production vs time. Growth usually starts slowly, as only the bold and/or the rich can afford, psychologically and financially, to explore the new invention. Then if the product is useful, acceptance grows exponentially. Increased production lowers costs, further accelerating the demand. Eventually, the market is saturated and demand slows to the replacement market. The technology is said to have matured. A major improvement, such as the development of color capability in television, may start the cycle over again. In addition to charting production and popular acceptance in this manner, technical progress can be similarly displayed. Figure 1 shows the speed history of transport aircraft. From 1928 to 1958, speed increased fivefold; the beginning of the jet age in 1958, however, established speed levels that have shown little change in the past 20 years. We have known how to increase speed above the typical airline cruise Mach numbers of 0.80-0.84 for decades, but we have not known how to substantially increase these speeds while simultaneously complying with the other major aircraft trend characteristic, namely, ever decreasing cost. Figure 2 shows the relative direct operating cost per seat mile from the DC-3 in 1936 to the Boeing 747 and DC-10 of the present. The standard 707/DC-8 aircraft have a relative cost value of 1.0. This chart has been constructed on an approximate constant dollar basis by using the cost ratios between one aircraft and the one proceeding it, as determined at the time of the aircraft's development. The smaller aircraft, such as the DC-9-30, show costs for their own shorter ranges which are similar to the larger aircraft with the same technology at the same short range, but only because they are designed for these much shorter ranges. Normally, increasing size decreases seat-mile cost up to 350-400 passenger capacities, after which this trend flattens out. The trend toward improved operating cost is strong and steady with only the Boeing Stratocruiser, the DC-7, and the Comet rising above the curve. The message to be learned from 50 years of aircraft history is clear. Successful aircraft have almost always had equal or lower operating cost compared to their predecessor, while offering service improvement in either speed, range, comfort, or combinations of them. In some cases, they have offered a significantly different size suitable to certain markets. The exceptions have offered a unique service at a moderately higher (10-15%) direct operating cost—and their success was generally limited. The rapid improvement in speed, the main commodity offered by aircraft, together with comparable gains in range and comfort, and the cost decrease led to the huge growth in air travel shown in Fig. 3 from Ref. 2 and in aircraft capacity shown in Fig. 4 from Ref. 1. As an industry, we became accustomed to rapid technical progress, imposing technological functional obsolescence on each succeeding type within two to seven years. Table 1 shows the chief technological developments that enabled each generation to reign supreme—although usually only for a brief period. Not listed specifically but continuing throughout the entire period have been significant improvements in airfoil design, flap systems, structural materials, and increasingly sophisticated methods of detail design and manufacture. The enormous contributions of avionics to aerial navigation, both en route and in the terminal area, were essential to the growth and safety of the air transport system. Great strides have been made in the electrical, hydraulic, pneumatic, and mechanical systems, which have permitted greater capability with reduced weight and exceedingly high reliability. But from the overall airplane design point of view, the items listed in Table 1 were most significant in making each succeeding design possible. Except for the World War II period, a first-line aircraft held that position for no more than six to seven years. Technological functional obsolescence was the way of life

9004 Background: Patients receiving treatment for cancer can experience a diminution of their cognitive abilities which can persist for many years after. The present study examined the potential of modafinil as a cognitive enhancer on memory and attention in a randomized clinical trial in breast cancer patients following completion of treatment. Methods: Breast cancer patients who reported a score of = 2 on the Brief Fatigue Inventory (BFI) an average of 22.8 months following completion of chemotherapy were enrolled. In Phase 1, patients received 200mg modafinil open-label once daily for 4 weeks. In Phase 2, patients with a positive response following Phase 1 were randomized either to an additional 4 weeks of modafinil or to placebo. Tests of memory and attention selected from the Cognitive Drug Research (CDR) computerized cognitive assessment were performed at baseline (before modafinil) and after completing Phase 1 and 2. The difference between scores at baseline and scores at Phase 1 and Phase 2, were subjected to a Wilcoxon's signed rank test. Results: Of the 82 women enrolled, 68 completed all 3 CDR assessments in the study (range=33–83 years, median age=54 years). At the end of Phase 1 (week 4), modafinil had a significant effect on the Speed of Memory Index (p=0.0047) and the Digit Vigilance Test (p=0.0014) but showed no significant effect on Quality of Working Memory (p=0.3528) nor on Power of Attention (p=0.8953). At the end of phase 2 (week 8), the group that continued modafinil demonstrated improved Mean Continuity of Attention (p=0.0002) compared with the placebo group and also demonstrated significantly greater improvements in Quality of Episodic Secondary Memory relative to placebo (p&lt;0.005). This improvement was observed at week 4, and was maintained throughout the study. Finally, continued modafinil demonstrated significantly greater improvement in Speed of Memory relative to placebo (p=0.009). Conclusions: Modafinil provides significant improvements in attention and speed of memory for breast cancer patients following their treatment of cancer. Although further study is needed, these findings suggest that modafinil may enhance quality of life in this patient population. Supported by a grant from Cephalon, Inc and NCI Grants U10-CA37420 and R25- CA102618. No significant financial relationships to disclose.

This work presents an FPGA implementation of FIR filter based on 4:2 compressor and CSA multiplier unit. The hardware realizations presented in this pa per are based on the technology-dependent optimization of these individual units. The aim is to achieve an efficient mapping of these isolated units on Xilinx FPGAs. Conventional filter implementations consider only technology-independent optimizations and rely on Xilinx CAD tools to map the logic onto FPGA fabric. Very often this results in inefficient mapping. In this paper, we consider the traditional CSA-4:2 compressor based FIR filte rs and restructure these units to achieve improved integration levels. The technology optimized Boolean networks are then coded using instantiation based coding strategies. The Xilinx tool then uses its own optimization strategies to further optimize the networks and generate circuits with high logic densities and reduced depths. Experimental results indicate a significant improvement in performance over traditional realizations. An important property of technology-dependent optimizations is the simultaneous improvement in all the performance parameters. This is in contrast to the technology-independent optimizations where there is always an application driven trade-off between different performance parameters.

In the implementation process of a convolution neural network (CNN)-based object detection system, the primary issues are power dissipation and limited throughput. Even though we utilize ultra-low power dissipation devices, the dynamic power dissipation issue will be difficult to resolve. During the operation of the CNN algorithm, there are several factors such as the heating problem generated from the massive computational complexity, the bottleneck generated in data transformation and by the limited bandwidth, and the power dissipation generated from redundant data access. This article proposes the low-power techniques, applies them to the CNN accelerator on the FPGA and ASIC design flow, and evaluates them on the Xilinx ZCU-102 FPGA SoC hardware platform and 45 nm technology for ASIC, respectively. Our proposed low-power techniques are applied at the register-transfer-level (RT-level), targeting FPGA and ASIC. In this article, we achieve up to a 53.21% power reduction in the ASIC implementation and saved 32.72% of the dynamic power dissipation in the FPGA implementation. This shows that our RTL low-power schemes have a powerful possibility of dynamic power reduction when applied to the FPGA design flow and ASIC design flow for the implementation of the CNN-based object detection system.

A novel architecture suitable for FPGA/ASIC implementation of a video scalar is presented. The scheme proposed here results in enormous savings of memory normally required, without compromising on the image quality. In the present work, SVGA compatible video sequence is scaled up to XGA format. The up scaling operation for a video sequence is carried out by scaling up the image input, followed by down scaling and filtering. The FPGA implementation of the proposed video-scaling algorithm is capable of processing high-resolution, color pictures of sizes up to 1024x768 pixels at the real time video rate of 30 frames/second. The design has been realized by RTL compliant Verilog coding, and fits into a single chip with a gate count utilization of two million gates. For lower resolution pictures, the mapped device can be scaled down. The present FPGA implementation compares favorably with another ASIC implementation.

The infrastructure of internet-of-things (IoT) and cyber-physical systems (CPS) is based on the security of communicated data. Here, lightweight cryptography plays a vital role in IoT/CPS resource-constrained environments. In this paper, we propose an architecture for the PRESENT lightweight block cipher and its VLSI implementations in an FPGA and ASIC. The input-output ports of the architecture are registered and datapath is based on 8-bit. It requires 49 clock cycles for processing of 64-bit plaintext with 80-bit user key. The FPGA implementation of the proposed architecture is done in Xilinx Virtex-5 device in comparison to an existing design improved performance has been obtained. Further, an ASIC implementation of the architecture is done in SCL 180 nm technology where gate equivalent (GE) of the design is 1608 GEs and area of chip is 1.55 mm2. At 100 MHz operating frequency, total power consumption of the chip is 0.228 mW. A throughput of 130.612 Mbps, energy 112.15 nJ, energy/bit 14.018 nJ/bit, and 0.813 efficiency is obtained.

Cylindrical phased array radar has an important role in low-altitude target surveillance, and signal processing is one of the important component modules of the radar system. Cylindrical radar as one kind of phased-array radar has the characteristics of full azimuth range of multi beam and huge data which makes high demands of signal processing. FPGA occupies an important position in radar signal processing because of its characteristics of high-speed and real-time. In this paper, signal processing scheme based on Xilinx's FPGA Kintex-7 and multi-core digital signal processor (DSP) is proposed, which mainly implements functions such as data reception, pulse compression, and moving target detection (MTD) processing etc. By comparing the actual results with the matlab simulation results, it is shown that this scheme has a good performance in stablility with fast processing speed. Moreover, it has obvious advantages in the design and provides great value for engineering.

The k-nearest neighbor (k-NN) is a popular non-parametric benchmark classification algorithm to which new classifiers are usually compared. It is used in numerous applications, some of which may involve thousands of data vectors in a possibly very high dimensional feature space. For real-time classification a hardware implementation of the algorithm can deliver high performance gains by exploiting parallel processing and block pipelining. We present two different linear array architectures that have been described as soft parameterized IP cores in VHDL. The IP cores are used to synthesize and evaluate a variety of array architectures for a different k-NN problem instances and Xilinx FPGAs. It is shown that we can solve efficiently, using a medium size FPGA device, very large size classification problems, with thousands of reference data vectors or vector dimensions, while achieving very high throughput. To the best of our knowledge, this is the first effort to design flexible IP cores for the FPGA implementation of the widely used k-NN classifier.

The effect of a drain offset structure on the operation speed of a tunnel field-effect transistor (TFET) ring oscillator is investigated by technology computer-aided design (TCAD) simulation. We demonstrate that the reduction of gate–drain capacitance by the drain offset structure dramatically increases the operation speed of the ring oscillators. Interestingly, we find that this capacitance benefit to operation speed is enhanced by the increase in band-to-band tunneling probability. The “synergistic” speed enhancement by the drain offset structure and the tunneling rate increase will have promising application to the significant improvement of the operation speed of TFET circuits.