Design and FPGA implementation of a video scalar with on-chip reduced memory utilization

This paper compares ASIC and FPGA implementations of two commonly used architectures for 2-dimensional discrete cosine transform (DCT), the parallel and folded architectures. The DCT has been designed for sizes 4x4, 8x8, and 16x16, and implemented on Silterra 180nm ASIC and Xilinx Kintex Ultrascale FPGA. The objective is to determine suitable low energy architectures to be used as their characteristics greatly differ in terms of cells usage, placement and routing methods on these platforms. The parallel and folded DCT architectures for all three sizes have been designed using Verilog HDL, including the basic serializer-deserializer input and output. Results show that for large size transform of 16x16, ASIC parallel architecture results in roughly 30% less energy compared to folded architecture. As for FPGAs, folded architecture results in roughly 34% less energy compared to parallel architecture. In terms of overall energy consumption between 180nm ASIC and Xilinx Ultrascale, ASIC implementation results in about 58% less energy compared to the FPGA.

The background subtraction is an important stage in the process of detecting moving objects in video sequences derived from stationary cameras of video surveillance systems (VSS cameras). variety of approaches to addressing the background selection problem in video sequences from stationary cameras of video surveillance systems has created the need for research on the choice of optimal algorithms. In this paper, we described the problem factors that complicate the background allocation process and described the basic background subtraction algorithms classifications. After analyzing the location of VSS cameras for certain objects within the Information and Telecommunication Systems of the State Border Guard Service and their inspection sectors, we have identified the features of the use of cameras from these systems. We researched the most common algorithms of background subtraction in video sequences, methods of comparative analysis and methodes for selecting optimal background subtraction algorithms in video sequences from stationary VSS cameras. We developed an improved efficiency index for the choice optimal algorithms for the background subtraction in video sequences derived from stationary cameras of video surveillance systems оn the basis method proposed Sobral Andrews and Vacavant Antoine in the Comprehensive review of subtraction algorithms evaluated using synthetic and real video. The essence of the improved method is that we propose to calculate the overall performance of the background subtraction algorithm using Matthews correlation coefficient, because this coefficient takes into account all possible variants of the matrix of algorithm responses (TP, TN, FP, FN). The proposed method was tested by calculating the results of the experimental study in the A comprehensive review of the subtraction algorithms evaluated using synthetic and real videos. As a result, we have developed the index of efficiency of an algorithm of background subtraction , that differs from that offered gathered Sobral Andrews and Vacavant Antoine (FSD), because it takes into account all options matrix classifier responses, and therefore is more accurate than the FSD.

In the implementation process of a convolution neural network (CNN)-based object detection system, the primary issues are power dissipation and limited throughput. Even though we utilize ultra-low power dissipation devices, the dynamic power dissipation issue will be difficult to resolve. During the operation of the CNN algorithm, there are several factors such as the heating problem generated from the massive computational complexity, the bottleneck generated in data transformation and by the limited bandwidth, and the power dissipation generated from redundant data access. This article proposes the low-power techniques, applies them to the CNN accelerator on the FPGA and ASIC design flow, and evaluates them on the Xilinx ZCU-102 FPGA SoC hardware platform and 45 nm technology for ASIC, respectively. Our proposed low-power techniques are applied at the register-transfer-level (RT-level), targeting FPGA and ASIC. In this article, we achieve up to a 53.21% power reduction in the ASIC implementation and saved 32.72% of the dynamic power dissipation in the FPGA implementation. This shows that our RTL low-power schemes have a powerful possibility of dynamic power reduction when applied to the FPGA design flow and ASIC design flow for the implementation of the CNN-based object detection system.

This paper presents an improved VLSI architecture of S-box for AES encryption system. Certain basic blocks in conventional architecture are replaced by efficient multiplexers and an optimized combinational logic to facilitate speed improvement. The proposed as well as conventional architecture are implemented in Xilinx FPGA and 0.18 μm standard cell ASIC technology. ASIC implementation indicates speed enhancement while maintaining constant area compared to conventional architecture. FPGA implementation also confirms speed improvement of about 0.6 ns along with low utilization of FPGA fabrics. Furthermore, there is significant power improvement (155 %) compared to conventional structure.

This work proposes a novel low power/area digital architecture for a Linear Program (LP) solver based on a recurrent (non-linear feedback) Neural Network (RNN), which is applied for spatial localization of sensors. Training data is not needed in our approach. We solve the primal and dual optimization problems for spatial localization with a single multi-functional data path which does not require matrix inversions. FPGA and ASIC implementations are presented which target a sensor (microrobot) localization problem in 2D using angle-of-arrival (AOA) measurements. The results show that the estimated locations (2D coordinates) are very close to the ground truth values in all tested scenarios. The proposed RNN has input and output layers, and a hidden layer with four neurons. FPGA implementation of the localizer in 180 nm process dissipates 180 mW of power at 1.5V and 31.25 MHz. When scaled to 128 neurons the performance is 13 Mop/sec/W for the same FPGA technology. The design has been also simulated in an ASIC 45 nm (PDK45 1V VDD) standard cell technology. With 128 neurons in the hidden layer the ASIC consumes 196.9 mW power at 516 MHz, which is equivalent to 677.165 Mop/sec/W.

The infrastructure of internet-of-things (IoT) and cyber-physical systems (CPS) is based on the security of communicated data. Here, lightweight cryptography plays a vital role in IoT/CPS resource-constrained environments. In this paper, we propose an architecture for the PRESENT lightweight block cipher and its VLSI implementations in an FPGA and ASIC. The input-output ports of the architecture are registered and datapath is based on 8-bit. It requires 49 clock cycles for processing of 64-bit plaintext with 80-bit user key. The FPGA implementation of the proposed architecture is done in Xilinx Virtex-5 device in comparison to an existing design improved performance has been obtained. Further, an ASIC implementation of the architecture is done in SCL 180 nm technology where gate equivalent (GE) of the design is 1608 GEs and area of chip is 1.55 mm2. At 100 MHz operating frequency, total power consumption of the chip is 0.228 mW. A throughput of 130.612 Mbps, energy 112.15 nJ, energy/bit 14.018 nJ/bit, and 0.813 efficiency is obtained.

Aim and Objective:The objective of this study was to optimize the threshold for discrete cosine transform (DCT) coefficients for near-lossless compression of Tc-99 m Dimercaptosuccinic acid (DMSA) scan images using discrete cosine transformation.Materials and Methods:Two nuclear medicine (NM) Physicians after reviewing several Tc-99 m DMSA scan images provided 242 Tc-99 m DMSA scan images that had scar. These Digital imaging and communication in medicine (DICOM) images were converted in the Portable Network Graphics (PNG) format. DCT was applied on these PNG images, which resulted in DCT coefficients corresponding to each pixel of the image. Four different thresholds equal to 5, 10, 15, and 20 were applied and then inverse discrete cosine transformation was applied to get the compressed Tc-99 m DMSA scan images. Compression factor was calculated as the ratio of the number of nonzero elements after thresholding DCT coefficients to the number of nonzero elements before thresholding DCT coefficients. Two NM physicians who had provided the input images visually compared the compressed images with its input image, and categorized the compressed images as either acceptable or unacceptable. The quality of compressed images was also assessed objectively using the following eight image quality metrics: perception-based image quality evaluator, structural similarity index measure (SSIM), multiSSIM, feature similarity indexing method, blur, global contrast factor, contrast per pixel, and brightness. Pairwise Wilcoxon signed-rank sum tests were applied to find the statistically significant difference between the value of image quality metrics of the compressed images obtained at different thresholds and the value of the image quality metrics of its input images at the level of significance = 0.05.Results:At threshold 5, (1) all compressed images (242 out of 242 Tc-99 m DMSA scan images) were acceptable to both the NM Physicians, (2) Compressed image looks identical to its original image and no loss of clinical details was noticed in compressed images, (3) Up to 96.65% compression (average compression: 82.92%) was observed, and (4) Result of objective assessment supported the visual assessment. The quality of compressed images at thresholds 10, 15, and 20 was significantly better than that of input images at P < 0.0001. However, the number of unacceptable compressed images at thresholds 10, 15, and 20 was 6, 38, and 70, respectively.Conclusions:Up to 96.65%, near-losses compression of Tc-99 m DMSA images was found using DCT by thresholding DCT coefficients at a threshold value equal to 5.

In this study, the optimal input parameters point spread function (PSF) and the number of iterations of the Richardson-Lucy algorithm were experimentally determined to restore Tc-99 m methyl diphosphonate (MDP) whole-body bone scan images. The experiment was performed on 60 anonymized Tc-99 m MDP whole-body bone scan images. Ten images were used for estimating the optimum value of PSF and the number of iterations to restore scintigraphic images. The remaining 50 images were used for validation of estimated parameters. The image quality of observed and restored images was assessed objectively using blind/referenceless image spatial quality evaluator (BRISQUE), mean brightness (MB), discrete entropy (DE), and edge-based contrast measure (EBCM) image quality metrics. Image quality was subjectively assessed by two nuclear medicine physicians (NMPs) by comparing the restored image quality with observed image quality and assigning a score to each image on the scale of 0-5. Based on BRISQUE, MB, DE, and EBCM scores, the restored images were significantly sharper, less bright, had more detailed information, and had less contrast around edges compared to the input images. The restored images had improved resolution based on visual assessment as well; NMPs assigned an average image quality score of 4.00 to restored images. Maximum resolution enhancement was noticed at PSF (size: 11 pixels, sigma: 1.75 pixels) and the number of iterations = 10. With the increase in the number of iterations, noise also gets amplified along with resolution enhancement and affects the detectability of small lesions; in the case of relatively low noisy input images, the number of iterations = 5 gave better results. Tc-99 m MDP bone scan images were restored to improve image quality using the Richardson-Lucy algorithm. The optimum value of the PSF parameter was found to be of size = 11 pixels and sigma = 1.75 pixels.

With the development of video surveillance in public safety field, there is an increasing research on person re-identification (re-id). In this paper, we address the image-to-video person re-id, in which the probe is an image and the gallery is consists of videos captured by nonoverlapping cameras. Compared with image, video sequence contains more temporal information that can be explored to improve the performance of re-identification system. However, it is challenging to model temporal information in the matching process of image-to-video person re-id. In this paper, we proposed a novel temporally memorized similarity learning neural network for this problem. In specific, the proposed network mainly consisted of two parts, including feature representation sub-network and similarity sub-network. In the first part, we adopted a convolutional neural network (CNN) to extract features from the input image. Given a video sequence of a person, features were first extracted from each its frame by using CNN and further forward to a long shot term memory (LSTM) network to encode the temporal information of video sequence. The outputs of LSTM were concatenated together as the feature vector of video sequences. Finally, the feature vectors of probe image and the video sequence were further forward to the similarity sub-network for distance metric learning. In the proposed framework, the feature representation and the similarity metric learning can be learned and optimized simultaneously. We evaluated the proposed framework on three public person re-id data sets, and the experimental results showed that the proposed approach is effective for the image-to-video person re-id.

An architecture for a single-chip VLSI implementation of a Wigner distribution signal processor is presented. ASIC implementation in CMOS technology is considered with complexity of 65000 gates, achieving a maximum throughput of 12 K 16-bit samples per second. The architecture takes advantage of the high level of integration and low power consumption achievable with CMOS technology thus eliminating clock skew and off-chip delays associated with chip-crossing penalties. By integrating the Wigner processor on the single chip, the implementation is made practical and attractive for processing acoustic signals. >

In this pilot study, we have proposed and evaluated pipelined application of the dynamic stochastic resonance (DSR) algorithm and block-matching 3D (BM3D) filter for the enhancement of nuclear medicine images. The enhanced images out of the pipeline were compared with the corresponding enhanced images obtained using individual applications of DSR and BM3D algorithm. Twenty 99m-Tc MDP bone scan images acquired on SymbiaT6 SPECT/CT gamma camera system fitted with low-energy high-resolution collimators were exported in DICOM format to a personal computer and converted into PNG format. These PNG images were processed using the proposed algorithm in MATLAB. Two nuclear medicine physicians visually compared each input and its corresponding three enhanced images to select the best-enhanced image. The image quality metrics (Brightness, Global Contrast Factor (GCF), Contrast per pixel (CPP), and Blur) were used to assess the image quality objectively. The Wilcoxon signed test was applied to find a statistically significant difference in Brightness, GCF, CPP, and Blur of enhanced and its input images at a level of significance. Images enhanced using the pipelined application of SR and BM3D were selected as the best images by both nuclear medicine physicians. Based on Brightness, Global Contrast Factor (GCF), CPP, and Blur, the image quality of our proposed pipeline was significantly better than enhanced images obtained using individual applications of DSR and BM3D algorithm. The proposed method was found to be very successful in enhancing details in the low count region of input images. The enhanced images were bright, smooth, and had better target-to-background ratio compared to input images. The pipelined application of DSR and BM3D algorithm produced enhancement in nuclear medicine images having following characteristics: bright, smooth, better target-to-background ratio, and improved visibility of details in the low count regions of the input image, as compared to individual enhancements by application of DSR or BM3D algorithm.

In on-street parking lots, it is very important to obtain the positions and license plate numbers of the vehicles for charging and management. Existing algorithms usually detect vehicles from an input image first, then localize their license plates, and finally recognize the license plate numbers. However, they are of high time and space complexity and cannot work if the vehicles or license plates are obscured. Therefore, this paper proposes an open-space vehicle positioning algorithm based on detection and tracking in video sequences. The work is as follows: (1) To reduce the time and space complexity, parallel detection of vehicles and license plates is carried out. Then, geometric matching is performed to accomplish the correspondences between them. (2) To track vehicles and license plates, this paper improves DeepSORT by combining with integrated voting based on the historical license plate library. (3) To accurately judge the vehicle behavior of entry or exit, a cumulative state detector is designed to increase the fault-tolerance of the proposed algorithm. The experimental results reveal that the proposed algorithm makes improvements in model parameters, inference speed, and tracking accuracy, demonstrating that it can be well applied to open-space vehicle positioning.

This paper proposes an efficient constant multiplier architecture based on vertical-horizontal binary common sub-expression elimination (VHBCSE) algorithm for designing a reconfigurable finite impulse response (FIR) filter whose coefficients can dynamically change in real time. To design an efficient reconfigurable FIR filter, according to the proposed VHBCSE algorithm, 2-bit binary common sub-expression elimination (BCSE) algorithm has been applied vertically across adjacent coefficients on the 2-D space of the coefficient matrix initially, followed by applying variable-bit BCSE algorithm horizontally within each coefficient. This technique is capable of reducing the average probability of use or the switching activity of the multiplier block adders by 6.2% and 19.6% as compared to that of two existing 2-bit and 3-bit BCSE algorithms respectively. ASIC implementation results of FIR filters using this multiplier show that the proposed VHBCSE algorithm is also successful in reducing the average power consumption by 32% and 52% along with an improvement in the area power product (APP) by 25% and 66% compared to those of the 2-bit and 3-bit BCSE algorithms respectively. As regards the implementation of FIR filter, improvements of 13% and 28% in area delay product (ADP) and 76.1% and 77.8% in power delay product (PDP) for the proposed VHBCSE algorithm have been achieved over those of the earlier multiple constant multiplication (MCM) algorithms, viz. faithfully rounded truncated multiple constant multiplication/accumulation (MCMAT) and multi-root binary partition graph (MBPG) respectively. Efficiency shown by the results of comparing the FPGA and ASIC implementations of the reconfigurable FIR filter designed using VHBCSE algorithm based constant multiplier establishes the suitability of the proposed algorithm for efficient fixed point reconfigurable FIR filter synthesis.

Lateral flow immunoassay (LFIA) is widely utilized in a variety of point-of-care-test (POCT) applications. In this paper, we discuss the development of an ASIC based strip reader controller for LFIA. The control algorithm was proposed and implemented in Verilog HDL and fabricated into ASIC with 0.18 μm CMOS technology. Functional validation on both FPGA and ASIC implementations were presented. The ASIC controller occupied 0.946 mm2 area and drawn only 2710.39 μW running at the frequency of 50 MHz. High sensitivity was achieved in the quantitative LFIA detection experiments, indicating this ASIC chip has fulfilled the requirement of operating an integrated and portable LFIA strip reading system.

Image fusion process is defined as extracting information and specific features from multiple input images and combining them into a single image which has all essential information. Image fusion methods which have been proposed in DCT domain are very convenient and time-saving in real-time applications. The fused output image of existing methods in DCT domain has low quality due to the side effects of their algorithms. In this article, an efficient and simple image fusion method using improved variance criteria is presented. The proposed method uses sharpened input images to make a larger difference between the variance of the corresponding input image's blocks. In addition, by adjusting two threshold values for recognizing the corresponding blocks which have close variance values, the quality of the output image is enhanced significantly. The results of conducting the proposed algorithm with gray-scale multi-focus images and evaluating the performance of the proposed method in comparison with the well-known methods confirm significant improvements in the quality of the output image. Finally, we demonstrate the simplicity of applying our method on color multi-focus images.