HEVC 2D-DCT architectures comparison for FPGA and ASIC implementations

Lateral flow immunoassay (LFIA) is widely utilized in a variety of point-of-care-test (POCT) applications. In this paper, we discuss the development of an ASIC based strip reader controller for LFIA. The control algorithm was proposed and implemented in Verilog HDL and fabricated into ASIC with 0.18 μm CMOS technology. Functional validation on both FPGA and ASIC implementations were presented. The ASIC controller occupied 0.946 mm2 area and drawn only 2710.39 μW running at the frequency of 50 MHz. High sensitivity was achieved in the quantitative LFIA detection experiments, indicating this ASIC chip has fulfilled the requirement of operating an integrated and portable LFIA strip reading system.

This paper presents a comparison with the conventional watermarking technique and the novel 5-stage pipelined implementation of DCT/IDCT which is used in digital image watermarking. The most common method of Discrete Cosine Transform (DCT)-based digital image watermarking which is used for image authentication and copyright protection is the transpose method. In this method the 2-Dimensional DCT is obtained by taking two 1-dimensional DCTs in series. The image pixel value is first divided into 8x8 blocks and the row-wise 1D DCT of each block is taken. The transpose of the blocks is then determined and a column-wise 1D DCT is ascertained which gives the 2D DCT of the data. The major advantage of this design is that, unlike the conventional DCT-based watermarking technique, this method uses a 5-stage pipeline which can bring about a speed increase of close to 500% over the conventional method which is naturally a great advantage. This technique has been tested on the standard ‘Lena’ image. Both visible and invisible watermarking is implemented in hardware. The design is done in Verilog HDL and the simulation is done in Modelsim 6.3b. Matlab is used to produce the binary data file which is the input to the 1D DCT module. The hardware implementation is done in Xilinx XC3S4000 FPGA. The results of the comparison are discussed in the concluding sections.

This paper presents an efficient approach for computing the N-point (N=2/sup n/) scaled discrete cosine transform (DCT) with the coordinate rotation digital computer (CORDIC) algorithm. The proposed algorithm is based on an indirect approach for computing the DCT so that the vector rotations are completely separated from the other operations and placed at the end of the DCT unit. As a result, unlike the other CORDIC-based DCT architectures, the proposed scaled DCT architecture does not require scale factor compensation. The number of CORDIC iterations is minimized through the optimal angle recoding method based on the three-value CORDIC algorithm. Although this three-value CORDIC algorithm results in different scale factors for different angles, this does not incur any extra hardware in the proposed scaled DCT architecture.

Integer Discrete Cosine Transform (DCT) reduces hardware complexity by eliminating floating point multiplication. Multiplier less multiple constant multiplication (MCM) is used to further optimize integer multiplication by replacing it with shifters and adders. As N-point DCT takes 25% of hardware complexity in high efficiency video coding (HEVC), further optimizing DCT in terms speed and power remains critical. Lately, an alternate real-valued DCT coefficients were proposed which reduced the amount of scaling used in Integer DCT coefficients. It achieved the low dynamic range, high speed and low power at same degree of approximation for DCT coefficients. In this paper, an effort is made to further approximate real-valued DCT coefficients of N-point DCT so that critical path due to MCM is reduced. Proposed approximate real-valued DCT coefficients has relatively good PSNR with optimized hardware compared to existing real-valued DCT coefficients. FPGA implementation of 1D-DCT architecture for 32-point DCT with approximate real-valued coefficients shows the reduction of 35% and 24% in area-delay product and power respectively.

In this paper, a low-power and high-modularity architecture for 8-point discrete cosine transform (DCT) computation is proposed. The coordinate rotation digital computer (CORDIC) based fast algorithm for DCT computation is derived using matrix decomposition. The sum-angle formula and double-angle formula is used to reduce the CORDIC types. Thus, a high-modularity DCT architecture is obtained by reusing the unique rotation angle CORDIC. The experimental results show that the proposed DCT architecture has lower power and higher modularity than other known architectures.

A hybrid adder-based distributed arithmetic (DA) architecture targeting a reconfigurable system-on-chip (rSoC) platform has been presented. The work exemplifies hardware comparisons of three DA based discrete cosine transform (DCT) algorithms based on pure-RAM, mixed-RAM and CORDIC-based processors. Preliminary investigation involved evaluation of the DCT algorithms on a heterogeneous composition of domain-specific memory and logic building blocks. The architectures were simulated for functional validation on ModelSim SE v6.0 and compliance testing of these architectures was performed using a self-testing testbench. The motivation was to illustrate the modularity, regularity, symmetry, and recursive-decomposition properties of transform vector-matrix computations for a case study of discrete cosine transforms using adder-based DA. Further, the paper overviews existing DCT architectures and previews future reconfigurable computing devices and contributes towards a novel conjecture on future directions in the reconfigurable hardware landscape. The embedded reconfigurable computation array presented in this paper has an intermediate-grain framework unlike the fine-grained nature of the current FPGAs.

Discrete cosine transform (DCT) is frequently used in image and video signal processing due to its high energy compaction property. Humans are able to perceive and identify the information from slightly erroneous images. It is enough to produce approximate outputs rather than absolute outputs which in turn reduce the circuit complexity. Numbers of applications like image and video processing need higher dimensional DCT algorithms. So the existing architectures of one dimensional (1D) approximate DCTs are reviewed and extended to two dimensional (2D) approximate DCTs. Approximate 2D multiplier-free DCT architectures are coded in Verilog, simulated in Modelsim to evaluate the correctness, synthesized to evaluate the performance and implemented in virtexE Field Programmable Gate Array (FPGA) kit. A comparative analysis of approximate 2D DCT architectures is carried out in terms of speed and area.

Demand of high quality image and video increases day by day. Quality is directly proportional to data size so there is need of compression. Discrete Cosine Transform (DCT) very popular in Latest Video codec standards because of its energy compaction and decorrelation properties. High Efficiency Video Codec (HEVC) is latest video codec technique which uses 4×4 to 32×32 basis vector for transformation. We implemented Input Adder Unit (IAU), Shift and Add Unit (SAU) and Output Adder Unit (OAU) of 1D and 2 D DCT of 4×4 and 8×8. This paper proposes SAU which has less Area Delay Product (ADP). Implementation is performed on Xilinx Spartan-3E FPGA, The proposed Hardware SAU takes 110 (4×4), 321(8×8) LUTs and 70(4×4), 212(8×8) slice registers with 494.56(4×4), 1143.216(8×8) ADP. By implementing our SAU into 1D as well as 2D DCT it takes 321 LUTs, 212 slice registers, 1410.4 ADP for 4×4 1D DCT architecture 1477 LUTs, 922 slice registers, 6489.9 ADP for 8×8 1D DCT architecture, 1284 LUTs, 847 slice registers, 5641.8 ADP for 4×4 2D DCT architecture 86 LUTs, 58 slice registers, 368.3 ADP for 8×8 2D DCT architecture. We also proposed Flexible Architecture from which User can switch between 4×4 and 8×8 Architecture according to application.

The Discrete Cosine Transform (DCT) is largely used for image and video compression in standards like JPEG and MPEG2. Its simplicity coupled with the fact that it can be computed faster than the Discrete Wavelet Transform (DWT) makes it an attractive option for image and video compression. Consequently a lot of research is in progress to determine novel architectures and algorithms for faster DCT computation having high throughput so that it can even be used for real time applications. For example, when transmitting and receiving videos, which have been compressed using MPEG2, one would like to receive the video, without any buffering delay. In other words, one requires such an architecture, which provides the DCTQ coeffecients at a consistent rate, with very low latency between two coeffecients. As such, a highly parallel and pipelined architecture employing 57 pipeline stages and using fast multipliers and adders is proposed in this work. The proposed DCT Processor is implemented in Spartan 3E FPGA.

In the implementation process of a convolution neural network (CNN)-based object detection system, the primary issues are power dissipation and limited throughput. Even though we utilize ultra-low power dissipation devices, the dynamic power dissipation issue will be difficult to resolve. During the operation of the CNN algorithm, there are several factors such as the heating problem generated from the massive computational complexity, the bottleneck generated in data transformation and by the limited bandwidth, and the power dissipation generated from redundant data access. This article proposes the low-power techniques, applies them to the CNN accelerator on the FPGA and ASIC design flow, and evaluates them on the Xilinx ZCU-102 FPGA SoC hardware platform and 45 nm technology for ASIC, respectively. Our proposed low-power techniques are applied at the register-transfer-level (RT-level), targeting FPGA and ASIC. In this article, we achieve up to a 53.21% power reduction in the ASIC implementation and saved 32.72% of the dynamic power dissipation in the FPGA implementation. This shows that our RTL low-power schemes have a powerful possibility of dynamic power reduction when applied to the FPGA design flow and ASIC design flow for the implementation of the CNN-based object detection system.

This paper presents an improved VLSI architecture of S-box for AES encryption system. Certain basic blocks in conventional architecture are replaced by efficient multiplexers and an optimized combinational logic to facilitate speed improvement. The proposed as well as conventional architecture are implemented in Xilinx FPGA and 0.18 μm standard cell ASIC technology. ASIC implementation indicates speed enhancement while maintaining constant area compared to conventional architecture. FPGA implementation also confirms speed improvement of about 0.6 ns along with low utilization of FPGA fabrics. Furthermore, there is significant power improvement (155 %) compared to conventional structure.

A novel architecture suitable for FPGA/ASIC implementation of a video scalar is presented. The scheme proposed here results in enormous savings of memory normally required, without compromising on the image quality. In the present work, SVGA compatible video sequence is scaled up to XGA format. The up scaling operation for a video sequence is carried out by scaling up the image input, followed by down scaling and filtering. The FPGA implementation of the proposed video-scaling algorithm is capable of processing high-resolution, color pictures of sizes up to 1024x768 pixels at the real time video rate of 30 frames/second. The design has been realized by RTL compliant Verilog coding, and fits into a single chip with a gate count utilization of two million gates. For lower resolution pictures, the mapped device can be scaled down. The present FPGA implementation compares favorably with another ASIC implementation.

This work proposes a novel low power/area digital architecture for a Linear Program (LP) solver based on a recurrent (non-linear feedback) Neural Network (RNN), which is applied for spatial localization of sensors. Training data is not needed in our approach. We solve the primal and dual optimization problems for spatial localization with a single multi-functional data path which does not require matrix inversions. FPGA and ASIC implementations are presented which target a sensor (microrobot) localization problem in 2D using angle-of-arrival (AOA) measurements. The results show that the estimated locations (2D coordinates) are very close to the ground truth values in all tested scenarios. The proposed RNN has input and output layers, and a hidden layer with four neurons. FPGA implementation of the localizer in 180 nm process dissipates 180 mW of power at 1.5V and 31.25 MHz. When scaled to 128 neurons the performance is 13 Mop/sec/W for the same FPGA technology. The design has been also simulated in an ASIC 45 nm (PDK45 1V VDD) standard cell technology. With 128 neurons in the hidden layer the ASIC consumes 196.9 mW power at 516 MHz, which is equivalent to 677.165 Mop/sec/W.

The infrastructure of internet-of-things (IoT) and cyber-physical systems (CPS) is based on the security of communicated data. Here, lightweight cryptography plays a vital role in IoT/CPS resource-constrained environments. In this paper, we propose an architecture for the PRESENT lightweight block cipher and its VLSI implementations in an FPGA and ASIC. The input-output ports of the architecture are registered and datapath is based on 8-bit. It requires 49 clock cycles for processing of 64-bit plaintext with 80-bit user key. The FPGA implementation of the proposed architecture is done in Xilinx Virtex-5 device in comparison to an existing design improved performance has been obtained. Further, an ASIC implementation of the architecture is done in SCL 180 nm technology where gate equivalent (GE) of the design is 1608 GEs and area of chip is 1.55 mm2. At 100 MHz operating frequency, total power consumption of the chip is 0.228 mW. A throughput of 130.612 Mbps, energy 112.15 nJ, energy/bit 14.018 nJ/bit, and 0.813 efficiency is obtained.

The Discrete Cosine Transform (DCT) is one of the most widely used techniques of transforms in digital signal processing. It is the main algorithm in image and video coding systems. In this paper, we propose an algorithm which generates enhanced Cordic based Loeffler DCT architectures for angle’s precision degrees ranging from 10−1 to 10−7. High level PSNR, area and power estimators have been proposed to make a trade-off between consumption and image quality. An optimal architecture has been retained for its low complexity, low power and high PSNR. The complexity of this architecture is the lowest among the conventional DCT architectures even the BinDCT which is a reference in terms of reduced complexity. The selected architecture has also the closest PSNR to the reference Loeffler-DCT architecture without a substancial loss of power.