Block co-polymerized polyimide resists for KrF lithography and EB lithography with high dry etching resistance

Surface damage in Si substrates created by Ar-ion milling or by reactive-ion etching in CF4, CHF3, Cl2, SiCl4, or SiF4 has been investigated. Metal-oxide-semiconductor capacitors were fabricated on the etched Si substrates, and the interface-state densities were obtained from capacitance-voltage measurements. Interface states generated by the dry etching processes were strongly dependent on the etching gas and the bias voltage. Carbon-based gases (CF4, CHF3) induced more interface states than those without carbon. For the carbon-based gases, Si samples etched in CHF3 showed lower densities of interface states than samples etched in CF4 under the same conditions. Generation lifetime measurements indicated that samples with large densities of interface states also had short lifetimes. Measurements of oxidation-induced stacking faults caused by dry etching were consistent with both the interface-state and lifetime measurements. Thermal annealing of the etched wafers was not effective in reducing the surface damage. The measured interface states on the dry etched Si substrates could be lowered to their pre-etched levels by removing at least 500 Å of the etched surface by wet chemical etching.

Self-assembly block copolymers have drawn a lot of attention for its great potential on critical dimension (CD) control and line-edge roughness (LER) reduction, which become more and more crucial as the CD of transistors is only tens of nanometers nowadays. In this study, lamellar-forming poly(styrene-b-methyl methacrylate) copolymer which fabricates line patterns was chosen for its ability to provide higher aspect ratio and vertical sidewall profile in template stage, thus more suitable for the following etching process to substrate. A dry plasma etching process using pure oxygen and pure argon plasma as example chemical etching gas and physical etching gas, respectively, was studied. Etching selectivity and lateral etch rate, which are responsible for the final template height and CD loss, had been characterized on a capacitive reactive ion etching tool. The templates formed by the proposed process had high aspect ratios, excellent pattern fidelity, and low LER values. The PS lateral etch rate was small enough to provide a wide process window for retaining the CD of the pattern during the template forming process. Subsequent silicon etching using the PS template made by dry etching process yielded a steep and smooth sidewall profile.

The growth of nanocrystalline diamond films having an appropriate surface smoothness for nanoscaled ultrafine patterning was investigated. The surface smoothness of polycrystalline diamond films was controlled by introducing nitrogen (N2) gas at concentrations ranging from 0 to 1.0% into the gas mixtures of methane (CH4) and hydrogen (H2) on microwave plasma-assisted chemical vapor deposition (MPCVD). The added 1.0% N2 with 10% CH4 in the gas phase yielded the desired diamond film with the smoothest surface among the conditions. An N-doped nanocrystalline diamond film was fabricated by nanoscaled ultrafine patterning by e-beam lithography followed by reactive ion etching (RIE). As a mask material in RIE, we found that a chemical vapor-deposited amorphous silicon nitride film is appropriate. A mixture consisting of oxygen and a small amount of tetrafluoro carbon was used as the etching gas. We succeeded in achieving a minimum line width of 100 nm in the N-doped nanocrystalline diamond film with our fabrication process.

We report on an inductively coupled plasma (ICP) process using CH/sub 4//H/sub 2//O/sub 2/ chemistry which have been studied for a self-aligned HBT technology. A very low bias voltage is used to reduce the induced damages. The study has concerned the ion flux characteristics: ion current and ion energy. Surface morphology, pattern profile, etch rates and induced damages were investigated as functions of ion energy and density for an optimized ICP reactor configuration. A comparison is made with an ICP process using a SiCl/sub 4/ chemistry. Finally, a selective process allowing one to attempt an almost full dry etching self-aligned process for HBT applications is described.

Volatile species produced during CH4/H2 and CH4/H2/Ar electron cyclotron resonance (ECR) reactive ion etching (RIE) of InP and GaAs at pressures of 2 mTorr have been investigated with secondary ion mass spectrometry diagnostics. A CH4/H2 ECR plasma with −120 V rf bias on the sample stage is found to etch InP but not GaAs. However, etching of GaAs does occur at this bias if the CH4/H2 mixture is diluted with Ar, showing the importance of physical bombardment to ‘‘activate’’ the GaAs surface. Group V hydrides are usually considered the most dominant volatile products in hydrocarbon RIE. In this work, it is shown that Ar dilution of a CH4/H2 mixture significantly increases the proportion of group V organometallic to hydride species in both GaAs and InP etching. More important, the main group III volatile ions from this etching process have been positively identified for the first time as In(CH3)+2 and Ga(CH3)+2 ions in InP and GaAs etching, respectively. Finally, the application of volatile product identification to end-point detection is demonstrated with a depth resolution better than 50 Å.

In this study, the indium tin oxide (ITO) was etched by an inductively coupled plasma (ICP) etcher using Cl 2 /C 2 H 4 /Ar as the etching gases. The etch rates were studied as a function of RF power, inductively coupled plasma (ICP) source power, working pressure and gas mixing ratio. We found that the RF Power plays a dominant role in the elevation of the etch rates, which indicates that the ITO etching in this study is a physical mechanism dominated etching. The state of the photoresist (PR) was observed after each experiment. As expected, the high power, which generally leads to a high etch rate, would distort the PR mask, resulting in a bad etched profile of the sample. Through research, we got a relatively high etch rate (∼ 200nm/min) with the shape of PR mask remain undistorted. The profile, which includes the morphology of the film sidewall and surface after the etching process, was sensitive to the gas mixing ratio. We adjusted the gas mixing ratio, and observed the profile using a scanning electron microscope (SEM), then optimal morphology was get as the Cl 2 /C 2 H 4 /Ar at the value of 30sccm/7sccm/50sccm.

Up until the late 1960s, chemical etching, also called wet solvent etching, was the key technology to integrated circuit manufacturing. Indeed, from the standpoint of manufacturing, wet etching provides low cost and often infinite selectivity. But, inherent limitations in wet etching preclude the use of this technique for micron and submicron pattern sizes. The most serious limitation is that of isotropic etching, which results in undercutting of the mask material and hence limits the minimum size of the pattern. To obtain high-density packing of microelectronic circuits, anisotropic etching is essential. By the early 1970s, CF /02 dry etching was widely adopted for patterning. It was widely recognized that dry etching offered the possibility of a vertical etch rate that greatly exceeded the horizontal etch rate (namely anisotropic etching). As a result, these dry etching techniques, which can generate anisotropic etch profiles, came into prominence. Dry etching soon began to appear in IC fabrication. However, these dry etching technologies, like wet processes, had their resolution limited by undercutting, and other, even more anisotropic etching techniques appeared. Among these were reactive ion etching (RIE). The RIE technique which has been widely adopted for IC fabrication until now provides moderate selectivity, etch rate and high anisotropy. In the mid-to-late 1970s, research began on a dry etch technique which would combine the positive features of RIE with directional bombardment of the surface by ions accelerated through electrostatic sheaths. Figure 1.1 shows how integrated circuits have evolved and how the number of individual components per circuit has increased with time. It is seen in the figure that the component density of IC circuits has doubled every year and this yearly doubling rate has been maintained from the first IC in 1960 until recently. At the same time, the design feature size has shrunk from 6 μm to 0.8 μm in the last 15 years, and the smallest dimensions are expected to decrease to 0.1 μmin the near future.

In this work, we present a planarization concept for epitaxial SiC trench structures involving reactive ion etching (RIE) and inductive coupled plasma (ICP) dry etching. The general idea is to transfer the flat surface from spun-on BCB/photo-resist layers to deposited silicon dioxide and finally to bulk SiC by applying process conditions with the same etch rate for the different materials. In this way several microns of unwanted material can be removed and planar SiC surfaces are obtained. With this method trench structures filled by epitaxial re-growth can be planarized with smooth surfaces and good homogeneity over the wafer. Cost-efficient device manufacturing can be achieved by using standard semiconductor process equipment. This technology makes it possible to manufacture advanced epitaxial SiC material structures for devices such as trench JBS diodes and double-gate trench JFETs.

Recently, DNA properties have been investigated to realize new functional biodevices. However, there are few reports on DNA nanopatterning to make bionanodevices. Therefore, we have attempted DNA nanopatterning by using a nanoimprint method. On a glass substrate coated with poly-L-lysine, which is known as a material for DNA immobilization by UV radiation, about 100 μl of a 1μg∕μl DNA solution was applied and was dried at 60 °C for an hour, and was irradiated by UV for 2 min. Further 4% polyvinyl alcohol (PVA) solution was coated on the substrate. The substrate was imprinted at 100 °C and 6 MPa for 5 min, and a mold was applied with a SiO2 on Si substrate fabricated by electron-beam lithography and dry etching. Etching of the DNA substrate was done by reactive ion etching in O2 atmosphere. Finally, the PVA layer washed down by water, and the DNA nanopatterning was obtained.

Dry etching utilizing showered electron beam assisted etching

An experimental study of the reactive ion etching (RIE) of GaP using BCl 3 plasma processing

Nano-pattering process by low-voltage electron beam lithography based on microcolumn with beam energy of 500 eV has been developed. Low kV exposure provides the advantages of high sensitivity, reduced charging, and a lack of proximity and heating effects. However a low-voltage electron beam has very thin penetration range. At 500 V, the penetration range is less than 20 nm, while typical resist thickness is > 200 nm. A resist process with bilayer scheme, 17 nm-thick PMMA resist on 100 nm-thick SiO₂ layer, and wet etch method was demonstrated for 250 nm line patterns transfer to Si substrate. The process was applied to fabricate periodic grating patterns on a silicon substrate. The results of nano-pattern process by low energy microcolumn lithography will be discussed in detail.

The research on millimeter-wave circuits is driven by applications such as radar imaging and wideband communications. For some applications SiGe hetero junction bipolar transistors (HBTs) are limited in output power, determined by the physical properties of silicon. For SiGe devices with transit frequencies of 180 GHz a breakdown voltage BVCEO of 2.0 V can be measured. The increase in breakdown voltage means always a decrease in transit frequency. On the other hand, silicon is the leading material of modern semiconductor technology. It offers a high level of integration density and yield. SiGe-HBT device speed has increased to hundreds of gigahertz, however limited in output power compared to III-V semiconductor devices. Thus, merging the qualities of both III-V and Si technology will enable a new class of high-performance ICs.Our approach combines a 3” InP-DHBT transferred-substrate process [1] with a SiGe-BiCMOS process [2]. At first, silicon and InP wafers are processed separately. The silicon wafer runs through the complete production process with front-end and back-end in a 0.25 µm BiCMOS process with a five metal layers aluminum/tungsten back-end using silicon dioxide as interlayer dielectric and an additional tungsten local interconnect. The back-end-process was specially adapted for the following wafer bond process by planarization of the topmost metal (TM2) level. The InP wafer has a semi-completed front-end and one metal level of gold and benzocyclobutene (BCB) as the dielectric. At this stage the front-to-front bond process is performed (see Fig. 1 a). The ground metallization (Gd) of the InP wafer is embedded in BCB to achieve a surface step height of less than 100 nm. Prior to wafer bonding both wafers are spin coated with BCB. After a BCB curing process the two wafers are aligned and bonded. After the bond process the InP substrate is etched by HCl to expose the InP-DHBT structures (see Fig. 1 a). The vias between the InP and SiGe-BiCMOS structures are formed by inductively coupled plasma (ICP) reactive ion etching (RIE) dry etching through the BCB using SF6. Then they are electrically connected using a gold electroplating process (see Fig. 1 b).To demonstrate the capabilities of the heterointegration scheme an integrated signal source at 164 GHz was designed and fabricated [3]. It is an example of the different combinations of BiCMOS and InP circuit building blocks. It is shown in Fig. 2. The source consists of a fundamental voltage-controlled oscillator (VCO) in BiCMOS technology (left side in Fig. 2) which is interconnected by an optimized high frequency via transition to a doubler-amplifier combination in InP technology (right side of Fig. 2).Recently, the influences of the wafer bonding and the finalization of the InP-DHBT process on SiGe devices were investigated. It was found that the impact on the BiCMOS devices is rather small. The forward Gummel plot of a SiGe-HBT before and after hetero integration is shown in Fig. 3. There is a slight increase of the base current at low emitter-base voltages caused by leakage currents due to electrostatic discharges in etching processes in the post bonding procedure. But these changes are marginal. Nevertheless, options to remove these effects are being discussed, such as moderate anneal sequences (the post-fabrication temperature is limited to below 250°C due to the presence of BCB) and modifications to the post-waferbonding plasma etch recipes.

The effect of increasing photoresist (PR) thickness on the inductively coupled plasma (ICP) dry etched characteristics of a 6″ (c.15 cm) molecular beam epitaxy Hg1−x Cd x Te/Si wafer is investigated. It is determined that the Hg1−x Cd x Te etch rate (ER) does not vary significantly with a change in the PR thickness. Also, the vertical ER of the PR is seen to be independent of the PR thickness, but the lateral ER is seen to reduce significantly with increased PR thickness. Indeed, very little reduction in the pixel mesa area post-dry etch is seen for the thicker PR. Consequently, the trench sidewall angle is also seen to vary as a function of the PR thickness. Since ICP is the more attractive choice for dry etching Hg1−x Cd x Te, this simple, cost-effective way to extend the capabilities of dry etching (larger mesa top area post-dry etch, ability to create tailor-made trench sidewall angles for optimal conformal passivation deposition, and potential for reduced dry etch damage) described here would allow for the fabrication of next generation infrared detectors with increased yield and reduced cost. Although similar results have been presented using the electron cyclotron resonance system to dry etch Hg1−x Cd x Te, to the best of our knowledge, this is the first time that such results have been presented using an ICP system.

The undoped stacked GeSn channels without parasitic Ge channels are realized by a radical-based highly selective isotropic dry etching. Heavily doped Ge sacrificial layers can reduce S/D resistance and the undoped GeSn channels can increase the channel mobility. SS=89mV/dec and ION =42μA per stack (10.5μA per sheet) at VOV =VDS =−0.5V are achieved for the undoped 4-stacked 12nm-thick nanosheets with 120nm gate length and the width larger than 50nm. The etching selectivity and the channel uniformity are highly improved by the dry etching as compared to H2 O2 wet etching. Both dry etching and undoped channel are essential to obtain stacked wide nanosheets with high performance.