Planarization of Epitaxial SiC Trench Structures by Plasma Ion Etching

We have developed a series of block co-polymerized polyimides for KrF lithography and EB lithography. Block co-polymerization is a synthesis method to control molecular structures. We have developed solvent soluble polyimides in powdered form. We can use these polyimides for dielectric materials in devices, and also can use as a dry etching mask in semiconductor processes. Here we report the details of dry etching properties for the block co-polymerized polyimides by reactive-ion-etching (RIE) using fluoride and chloride gases, typically used for Si etching and GaAs etching, respectively. Etching rates for EB exposed polyimide, photosensitive polyimide, novolac standard photoresist and Si at the condition of 80 W RF power and 60 sccm SF₆ gas flow, were measured as < 1 nm/min, 1.7 nm/min, 34 nm/min and 31 nm/min, respectively. We also checked the etching rate for EB exposed polyimide, photosensitive polyimide, novolac standard photoresist and GaAs at the condition of 50 W RF power and 3 sccm Cl₂ gas flow in the inductive coupled plasma (ICP) RIE, were measured as < 1 nm/min, 50 nm/min, 120 nm/min and 500 nm/min, respectively. Dry etching selectivity of EB exposed polyimide to Si is more than 31, and dry etching selectivity to GaAs is more than 500. These values are much higher compared to novolac standard photoresist. The high resolution EB exposed polyimide is promising for nano-patterning as stable dry etching mask. RIE resistance for polyimide photoresist is 20 times more than novolac standard photoresist for SF₆ etching gas, and more than twice for Cl₂ etching gas.

In this work, we introduce an effective yet low cost method to improve the Ohmic contact in the AlGaN/GaN HEMT. Even with high temperature annealing, the source/drain contact shows Schottky behavior with a large turn-on voltage (V ON ) which limits the ON current of the transistor, especially under low operation voltage. An extra Ar reactive ion etching (RIE) performed after the O 2 RIE is found to largely improve the source/drain contact. The Schottky contact with high V ON is converted to Ohmic contact with negligible V ON under a moderate Ar RIE power. The relation between the Ar RIE power and V ON is studied systematically revealing an interesting trend. This effect is due to the recess of the AlGaN layer by the Ar RIE, similar to that etched by the Cl-based inductive coupled plasma (ICP). Compared to Cl-based ICP, Ar RIE has lower production cost, better environmental compatibility and is less hazardous to human health.

Nanotip arrays with high aspect ratio, which have attracted much attention due to their potential applications, have been fabricated by many methods. Dry etching combined with self-assembly masks is widely used because of the convenience of dry etching and high throughput of self-assembly. In this paper, we report a method combining Cesium Chloride (CsCl) self-assembly with inductively coupled plasma (ICP) dry etching to fabricate silicon nanotip arrays with high aspect ratio and silicon nanotip arrays with aspect ratio 15 have been achieved after optimization of all parameters.

High rate dry etching of (BiSb)2Te3 film by CH4/H2-based plasma

Dry etching or plasma-assisted etching (ion beam milling, plasma etching and reactive sputter etching) has become an indispensable preparation technique for high resolution pattern transfer in IC manufacturing and other areas of microfabrication. Etching can either be due to the purely physical process of momentum transfer from ions to the solid surface (e.g. inert ion etching) or due to chemical reactions of reactive species, produced in the plasma, with the solid surface resulting in a volatile reaction product (e.g. plasma etching in a barrel reactor). However, in most dry etching methods both effects play a major role and it is possible to optimize etch selectivity and the shape of the etched profile by a proper choice of parameters.

The research on millimeter-wave circuits is driven by applications such as radar imaging and wideband communications. For some applications SiGe hetero junction bipolar transistors (HBTs) are limited in output power, determined by the physical properties of silicon. For SiGe devices with transit frequencies of 180 GHz a breakdown voltage BVCEO of 2.0 V can be measured. The increase in breakdown voltage means always a decrease in transit frequency. On the other hand, silicon is the leading material of modern semiconductor technology. It offers a high level of integration density and yield. SiGe-HBT device speed has increased to hundreds of gigahertz, however limited in output power compared to III-V semiconductor devices. Thus, merging the qualities of both III-V and Si technology will enable a new class of high-performance ICs.Our approach combines a 3” InP-DHBT transferred-substrate process [1] with a SiGe-BiCMOS process [2]. At first, silicon and InP wafers are processed separately. The silicon wafer runs through the complete production process with front-end and back-end in a 0.25 µm BiCMOS process with a five metal layers aluminum/tungsten back-end using silicon dioxide as interlayer dielectric and an additional tungsten local interconnect. The back-end-process was specially adapted for the following wafer bond process by planarization of the topmost metal (TM2) level. The InP wafer has a semi-completed front-end and one metal level of gold and benzocyclobutene (BCB) as the dielectric. At this stage the front-to-front bond process is performed (see Fig. 1 a). The ground metallization (Gd) of the InP wafer is embedded in BCB to achieve a surface step height of less than 100 nm. Prior to wafer bonding both wafers are spin coated with BCB. After a BCB curing process the two wafers are aligned and bonded. After the bond process the InP substrate is etched by HCl to expose the InP-DHBT structures (see Fig. 1 a). The vias between the InP and SiGe-BiCMOS structures are formed by inductively coupled plasma (ICP) reactive ion etching (RIE) dry etching through the BCB using SF6. Then they are electrically connected using a gold electroplating process (see Fig. 1 b).To demonstrate the capabilities of the heterointegration scheme an integrated signal source at 164 GHz was designed and fabricated [3]. It is an example of the different combinations of BiCMOS and InP circuit building blocks. It is shown in Fig. 2. The source consists of a fundamental voltage-controlled oscillator (VCO) in BiCMOS technology (left side in Fig. 2) which is interconnected by an optimized high frequency via transition to a doubler-amplifier combination in InP technology (right side of Fig. 2).Recently, the influences of the wafer bonding and the finalization of the InP-DHBT process on SiGe devices were investigated. It was found that the impact on the BiCMOS devices is rather small. The forward Gummel plot of a SiGe-HBT before and after hetero integration is shown in Fig. 3. There is a slight increase of the base current at low emitter-base voltages caused by leakage currents due to electrostatic discharges in etching processes in the post bonding procedure. But these changes are marginal. Nevertheless, options to remove these effects are being discussed, such as moderate anneal sequences (the post-fabrication temperature is limited to below 250°C due to the presence of BCB) and modifications to the post-waferbonding plasma etch recipes.

This thesis describes the development of a dry plasma etch smoothing technique to replace the conventional Chemical Mechanical Polishing process within a device manufacturing scheme in the semiconductor industry. An important semiconductor manufacturing process is 3D wafer packaging, which allows vertical stacking of wafer die. 3D wafer packing represents a significant component of the total wafer level processing cost. A critical step in the 3D packaging process flow is the Chemical Mechanical Polishing process. Replacement of the CMP process step with a corresponding dry etch can yield significant time and cost savings. This is achievable through reductions in metrology and wafer handling requirements and lower volumes of materials needed for plasma-etch based processes compared with CMP. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200 nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6 nm is demonstrated, which is comparable to a virgin silicon wafer. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where these surface scratches are falsely identified as defects. The quality of the plasma polished surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification process followed by a roughness reduction iteratively, to produce a smooth surface without visible grind marks. Further work describes the application of the smoothing process to microneedles, with the aim of improving the process flow. Smoothing of silicon carbide has been performed. Finally, an extension of the TSV reveal process is described, called extreme thinning, with the development of a predictive model to minimize final total thickness variation. Silicon smoothing can also be beneficial to this application.

Up until the late 1960s, chemical etching, also called wet solvent etching, was the key technology to integrated circuit manufacturing. Indeed, from the standpoint of manufacturing, wet etching provides low cost and often infinite selectivity. But, inherent limitations in wet etching preclude the use of this technique for micron and submicron pattern sizes. The most serious limitation is that of isotropic etching, which results in undercutting of the mask material and hence limits the minimum size of the pattern. To obtain high-density packing of microelectronic circuits, anisotropic etching is essential. By the early 1970s, CF /02 dry etching was widely adopted for patterning. It was widely recognized that dry etching offered the possibility of a vertical etch rate that greatly exceeded the horizontal etch rate (namely anisotropic etching). As a result, these dry etching techniques, which can generate anisotropic etch profiles, came into prominence. Dry etching soon began to appear in IC fabrication. However, these dry etching technologies, like wet processes, had their resolution limited by undercutting, and other, even more anisotropic etching techniques appeared. Among these were reactive ion etching (RIE). The RIE technique which has been widely adopted for IC fabrication until now provides moderate selectivity, etch rate and high anisotropy. In the mid-to-late 1970s, research began on a dry etch technique which would combine the positive features of RIE with directional bombardment of the surface by ions accelerated through electrostatic sheaths. Figure 1.1 shows how integrated circuits have evolved and how the number of individual components per circuit has increased with time. It is seen in the figure that the component density of IC circuits has doubled every year and this yearly doubling rate has been maintained from the first IC in 1960 until recently. At the same time, the design feature size has shrunk from 6 μm to 0.8 μm in the last 15 years, and the smallest dimensions are expected to decrease to 0.1 μmin the near future.

Channel fabrication technology has become increasingly important for microfluidic and nanofluidic devices. In particular, glass channels have high chemical and physical stability, high optical transparency, and ease of surface modification, so that there is increasing interest in glass microfluidic devices for chemical experiments in microfluidics and nanofluidics. For the fabrication of glass channels, especially those with a high aspect ratio (depth/width), lithography using a metal resist and dry etching have mainly been used. However, there are still issues involving the surface roughness of the etched channel and the low etching selectivity. In this study, a microchannel fabrication method with high etching selectivity that produces a smooth etched surface was developed. First, interference during dry etching by remaining Cr particles after the photolithography and Cr etching processes was assumed as the cause of the rough etched surface. Three different dry etching processes were introduced to verify this. In process 1 without removal of the Cr particles, the etched surface was not flat and had a 1 μm scale roughness. In process 2 where a cleaning process was included and high power etching was conducted, a smooth surface with a 1 nm scale roughness and a faster etching rate of 0.3 μm min−1 were obtained. For this high-power etching condition, the etching selectivity (fused silica/Cr) was relatively low at approximately 39–43. In process 3 with a cleaning process and low-power etching, although the etching rate was relatively low at 0.1 μm min−1, a smooth surface with 1 nm scale roughness (10 nm scale roughness deeper than 40 μm in the depth region) and a much higher etching selectivity of approximately 79–84 were obtained. The dry etching method presented in this study represents a significant contribution to microfluidics/nanofluidics for microchannel/nanochannel fabrication.

This work investigates the leakage and breakdown mechanisms in a Cu damascene structure with carbon-doped CVD extra low-k material (ELK, k=2.5) as intermetal dielectric. The effects of ash processing by inductively coupled plasma (ICP) and reactive ion etching (RIE) modes were extensively characterized. Due to the dominance of Frenkel-Poole (FP) emission in the leakage mechanism between Cu lines, we extracted for the first time the effective k through leakage measurements under various ash conditions. We demonstrate that RIE ash is promising to reduce leakage current, to improve dielectric breakdown, and to retain effective k for Cu/ELK applications. Finally, the mechanisms of ELK damages by ICP and RIE ash are explained.

Plasma (dry) etching is a key step in semiconductor device manufacturing processes whereby the resist pattern is transferred to a substrate. As the resist thickness is reduced to meet stringent transparency requirements in photolithography, the usage of fast etching material as BARC is considered to be increasingly critical in minimizing resist thickness loss in pattern transfer steps. Several models emphasizing correlation between polymeric structure and etch resistance based on empirical parameters have been developed but are hard to generalize. We have examined the reactive ion etch (RIE) properties of a variety of polymer groups including natural polymers, poly(styrenic)s, poly(acrylate)s, poly(olefin)s, poly(ester)s and several polymers grafted with UV light absorbing chromophores. With the assumption that in the etching processes the reactive species from plasma attack the polymeric materials at a molecular level instead of an atomic level, we have developed a model based on the contribution of chemical bonds in the polymer structure to predict etch rates. The present study shows that this model revealed marked correlations across polymer families for three different etch processes. This model has also proved to be an effective tool in predicting the etch behavior of polymers for use in BARCs.

Among rare-earth ion-doped crystals that are of high interest for quantum technologies, yttrium orthosilicate [Y2SiO5 (YSO)] crystal has demonstrated the longest coherence times. Etching optical guiding structures enables the creation of complex structures offering the advantage of technological scalability. We report on the dry etching of YSO crystal wafers performed by inductive coupled plasma (ICP) reactive ion etching. The material etching rate, the etch rate selectivity versus the material mask, and the etched side wall’s shape have been measured for various ICP process parameters and gas combinations including Ar-alone, Cl2:Ar, and Cl2:N2 plasma chemistry. These gas-combination choices have enabled identifying the etching mechanisms involved. Etching results have evidenced that Ar ions are the primary contributors for YSO etching, with Cl ions being also efficient, while Cl neutrals play a marginal role. ICP YSO etching is predominantly a physical process carried out by ions. Several ICP powers and RF powers have been investigated. The highest 80 nm/min etch rate is obtained under the Ar-alone plasma, but at the expense of trenching, while chlorine-based etching provides no trenching and smooth side walls. The choice of the dielectric material mask is also discussed.

Reactive ion etching of FePt using inductively coupled plasma

The effect of increasing photoresist (PR) thickness on the inductively coupled plasma (ICP) dry etched characteristics of a 6″ (c.15 cm) molecular beam epitaxy Hg1−x Cd x Te/Si wafer is investigated. It is determined that the Hg1−x Cd x Te etch rate (ER) does not vary significantly with a change in the PR thickness. Also, the vertical ER of the PR is seen to be independent of the PR thickness, but the lateral ER is seen to reduce significantly with increased PR thickness. Indeed, very little reduction in the pixel mesa area post-dry etch is seen for the thicker PR. Consequently, the trench sidewall angle is also seen to vary as a function of the PR thickness. Since ICP is the more attractive choice for dry etching Hg1−x Cd x Te, this simple, cost-effective way to extend the capabilities of dry etching (larger mesa top area post-dry etch, ability to create tailor-made trench sidewall angles for optimal conformal passivation deposition, and potential for reduced dry etch damage) described here would allow for the fabrication of next generation infrared detectors with increased yield and reduced cost. Although similar results have been presented using the electron cyclotron resonance system to dry etch Hg1−x Cd x Te, to the best of our knowledge, this is the first time that such results have been presented using an ICP system.

Evaluation of fluorinated polyimide etching processes for optical waveguide fabrication