Complexity-Preserving Transposition of Summing Algorithms: A Data Flow Graph Approach

Network teaching is to use computer equipment and Internet technology in the virtual space, through a certain method to implement the teaching method on the network, the perfection of the network teaching system can directly replace the traditional teaching method in the whole process of teaching. In order to solve the problem of system development, this paper carries out the demand analysis. First, the use of data flow graph technology, depicting information flow and data from the input to the output of the process of transformation; and then, the use of data dictionary technology, defining the relevant elements of the data flow diagram; finally, the use of tree structure diagram is represented by the administrator subsystem, teacher subsystem and student subsystem structure of the system. The requirement analysis system design the bridge of analysis and software, has laid a foundation for the system development.

The ULowell Data Flow Project combines dataflow hardware, dataflow software, and a data flow development environment. The hardware component, a data flow coprocessor card, utilizes seven NEC 7281 Image Pipelined Processors. Each chip models a static dataflow computation and is programmable. The coprocessor was designed and implemented by ULowell personnel and uses an AMIGA 2000 as a host. The software component currently consists of a library of data flow image processing algorithms and an evolving software development environment. Currently the image processing library includes typical imaging operations such as: edge enhancement, filtering, histogramming, and affine transformation. The software development environment (SDE) is depicted in Figure 1. The SDE contains a Data Flow Graph Editor which programmers use to design their data flow code. The data flow algorithm can then be converted directly into NEC data flow assembly code which is then assembled using the ULowell Data Flow Assembler. The assembler differs from NEC's assembler in that it can produce relocatable code. The object code output of the assembler is given to the Data Flow Resource Manager. The resource manager monitors the available resources within the chips. Thus, if a single process does not totally utilize a chip's table space or memory, then a second process may be concurrently loaded onto the same chip. The ability to have multiple data flow processes coexisting within a single chip is unique to the ULowell environment. The data flow resource manager can download and monitor code to either the hardware or to a software simulator/debugger. The simulator/debugger can monitor and trace data flow tokens as they proceed through the chip. Output of the simulator/debugger can be fed back into the data flow graph editior to visually trace token flow through the original program design. The last component of our SDE is a High Level Language translator which can compile programs written in SISAL, a high level language for parallel computation, down to NEC 7281 assembly language. We have already implemented the relocatable assembler, and the data flow resource manager. Prototype versions of the high level translator, simulator/debugger and graph/editor are currently being implemented.

This paper presents a cost-effective scheme for partitioning large data flow graphs. Standard data flow machine architectures are assumed in this work. The objective is to reduce the overhead due to token transfers through the communication network of the machine. When this scheme is employed on large graphs, the load distribution on the rings of the data flow machine is also improved. A canonical form of a data flow graph is introduced to establish the relationship between the communication overhead and the size reduction of the partition cut-set. General lower estimates on the overhead are derived in terms of processing and transmission delay parameters of the machine. The method uses heuristics and an evaluation function to guide the partition algorithm. Some implications of the proposed method on the organization of the data flow machines are discussed.

This paper explores the problem of identifying malicious code sections in applications for the Android. A method for analyzing Android applications is proposed, based on applying of static analysis using control flow graphs and data flow graphs. The paper formally describes the dependency relationships that are used to construct graphs, and also describes an algorithm that allows to identify malicious sections of code using the received graphs. The results of an experimental evaluation of the effectiveness of the proposed method are presented, demonstrated a high probability of detecting malicious portions of the code of Android applications.

Smart contracts on blockchain platforms are susceptible to security issues that can lead to significant financial losses. This study converts the Solidity code into abstract syntax trees and generates control flow graphs and data flow graphs. These graphs train a graph convolutional network model to detect security weaknesses. The proposed system outperforms traditional tools, achieving higher accuracy, recall, precision, and F1 scores when detecting weaknesses such as integer overflow/underflow, reentrancy, delegate call to the untrusted callee, and time-based issues. This study demonstrates that leveraging control and data flow analysis with graph neural networks significantly enhances smart contract security and provides a robust and reliable solution.

An Ameliorated Methodology for the Abstraction of Object Oriented Features from Software Requirements Specification

A system called net optimization and resource allocation (NORA) is introduced for the evaluation and programming of parallel signal processors, based on a data flow representation of the signal processing application. The main feature of this approach is that the scheduling and resource allocation can be done at compile time. It is made possible by the fact that most signal processing algorithms have constant data flow. The resulting hardware is much simpler because no overhead is needed for the real-time scheduling, as in usual data flow systems. Therefore a realization can easily be obtained using either commercially available components or VLSI technology. The proposed system comprises four main components: (1) a vector oriented data flow compiler for the translation of a high-level language description of algorithms into a data flow graph; (2) a critical path analysis for the evaluation of the minimal computation time of the algorithm, where block scheduling is assumed; (3) a schedule optimization for the determination of the minimal computation time under limited resources, not taking into account limitations imposed by the interconnection structure and temporary storage; and (4) a combined schedule optimization and resource allocation that maps a signal processing application onto a given hardware configuration and generates a formal microprogram.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In this paper we present a new approach to data analysis based on flow distribution study in a flow network. Branches of the flow graph are interpreted as decision rules, whereas the flow graph is supposed to describe a decision algorithm. We propose to model decision processes as flow graphs and analyze decisions in terms of flow spreading in the graph.

Aim of the new methodology proposed is to extract, from a behavioral circuit description, all information on the regularity of the computation. Array architectures optimally implement the extracted regular behavior. A high-level synthesis tool for such arrays has been defined. First, the problem of translating a hardware description language (either VHDL or Hardware C) into and internal representation useful for the exploration of different alternative architectures is afforded. Here the main problems relate to the different interpretations that can be given to an HDL description during the behavioral synthesis step. A set of design rules for writing the specifications has been identified. Then the internal design representation is studied. A hierarchical graph-based representation has been adopted which contains all information needed to identify possible regularities. The hierarchical structure is composed of a data flow graph (DFG) that holds information about data and operations performed and of a control flow graph (CFG) representing the condition clauses causing the choice of the computations to be performed. All information needed to identify the regular structures, can be derived from the DFG alone, while the information of the CFG is useful to correctly synthesize the control machine. The proposed high-level synthesis approach has been implemented into a module called Orpheus, which can be connected to the Olympus synthesis system.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

In the pursuit of massively multiplayer online games, efficient engines capable of processing sophisticated game scenarios are necessary to support large scale virtual worlds. By applying microprocessor microarchitectural design techniques to game server software design, functional parallelism inherent in complex game transactions can be exploited, augmenting server performance.In a given gaming scenario, complex game transactions can be modeled as data flow graphs. An individual graph represents the collective atomic operations of a particular transaction. Analysis of data flow graphs provides a mechanism that identifies opportunities for parallelism by exposing data dependencies.This poster presents an engine architecture that supports spatial and temporal parallel execution of complex game transactions expressed as data flow graphs. The engine takes advantage of data flow enhancement techniques such as dynamic out-of-order execution to achieve a high level of performance.

Applications in the signal processing domain are often modeled by data flow graphs which contain both dynamic and static data flow actors due to heterogeneous complexity requirements. Thus, the adopted notation to model the actors must be expressive enough to accommodate dynamic data flow actors. On the other hand, treating static data flow actors like dynamic ones hinders design tools in applying domain-specific optimization methods to static parts of the model, e.g., static scheduling. In this paper, we present a general notation and a methodology to classify an actor expressed by means of this notation into the synchronous and cyclo-static dataflow models of computation. This enables the use of a unified descriptive language to express the behavior of actors while still retaining the advantage to apply domain-specific optimization methods to parts of the system. In experiments we could improve both latency and throughput of a general data flow graph application using our proposed automatic classification in combination with a static single-processor scheduling approach by 57%.

The attractiveness of the flow-graph analysis of systems lies to a great extent in the ability to manipulate the graph by inspection. Nevertheless, in large flow graphs the inspection technique is often a shaky one for writing transmission equations. If one insists on using the flow-graph approach, a systematic mathematical means is needed to assure that no loops, paths, or contiguous conditions among loops and/or paths are missed. This paper describes an analytical-combinatorial method, which produces error-free transmission equations. Use is made of suitably modified vertex matrices and combinatorially developed path-vertex-loop matrices.

We define a graph based visual query language for object databases, called QUIVER. Most graph based query languages proposed in the literature view queries either as constraint (pattern) graphs or as data flow graphs. QUIVER, however allows constraints and data flow to be combined in queries. This combination of constraints and data flow is motivated by the need to support comprehensive object models, such as that proposed by the Object Data Management Group (ODMG). QUIVER supports all ODMG object model constructs, including computational constructs such as operations (methods). In addition, QUIVER supports computational query constructs such as subqueries and (aggregate) functions.

Using graph isomorphism for mapping of data flow applications on reconfigurable computing systems

In this paper, we investigate the theoretical foundation for the cost/precision trade-off of data flow graphs for verification. We show that one can use the theory of tree automata in order to characterize the loss of precision inherent in the abstraction of a program by a data flow graph. We also show that one can transfer a result of Oh et al. and characterize the power of the proof system of data flow proofs (through a restriction on the assertion language in Floyd-Hoare proofs).