Concurrent Core Test Based on Partial Test Set Reusing

A test pattern compression scheme for test data volume and application time reduction is proposed. While compression reduces test data volume, the increased number of internal scan chains due to an on-chip, fixed-rate decompressor reduces test application time proportionately. Through on-chip decompression, both the number of virtual scan chains visible to the ATE and the functionality of the ATE are retained intact. Complete fault coverage is guaranteed by constructing the decompression hardware deterministically through analysis of the test pattern set.

Scan design, providing a good test solution to sequential circuits, suffers large data volume, long test time and high test power problem. Recently, the random access scan (RAS) scheme offers a solution to alleviate the above problems (Baik et al., 2004). In this paper, based on RAS, a cocktail scan scheme is proposed and demonstrated to improve the test efficiency significantly. The scheme adopts a two-phase approach, firstly by using a cycle random scan test with a few random seed patterns to test the DUT and secondly, by using the RAS mechanism to test the circuit. Due to employment of a revised process and several strategies, namely, test response abundant, constrained static compaction, and bit propagation before test vector dropping, it is very effective in reducing bit flipping and test data volume, consequently, the test application time and power. Experimental results show that the scheme can achieve 86% reduction in test data volume and 10 times of speedup in test application time.

Testing chips is very critical to guarantee chips are fault-free before they are integrated in a system, so as to increase the reliability of the system. Although full-scan is a widely adopted design-for-test technique for LSI design and testing, the need for reducing the test data volume, scan-in power dissipation and test application time (VPT) of the full-scan designed chip is imperative. Based on the analysis of the characteristics of the variable-to-fixed run-length coding technique and the random access scan architecture, this paper presents a novel design scheme tackling all VPT issues simultaneously. Experimental results on ISCAS'89 benchmarks have shown on average 51.2%, 99.5%, 99.3% and 85.5% reduction in test data volume, average scan-in power dissipation, peak scan-in power dissipation and test application time, respectively.

This paper presents a new test data compression technique based on a compression code that uses exactly nine codewords. In spite of its simplicity, it provides significant reduction in test data volume and test application time. In addition, the decompression logic is very small and independent of the precomputed test data set. Our technique leaves many don't-care bits unchanged in the compressed test set, and these bits can be filled randomly to detect non-modeled faults. The proposed technique can be efficiently adopted for single- or multiple-scan chain designs to reduce test application time and pin requirement. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

We present a test resource partitioning (TRP) technique that simultaneously reduces test data volume, test application time and scan power The proposed approach is based on the use of alternating run-length codes for test data compression. Experimental results for the larger ISCAS-89 benchmarks and an IBM production circuit show that reduced test data volume, test application time and low power scan testing can indeed be achieved in all cases.

Test access mechanism (TAM) optimization and test data compression lead to a reduction in test data volume and testing time for SOCs. In this paper, we integrate for the first time both these approaches into a single test methodology. We show, how an integrated test architecture based on TAMs and test data decoders can be designed. The proposed approach offers considerable savings in test resource requirements. Two case studies using the integrated test architecture are presented. Experimental results on rest data volume reduction, savings in test application time and the low test pin overheads for a benchmark SOC demonstrate the effectiveness of this approach.

Design for Testability (DFT) based on scan and ATPG has been adopted as a reliable and broadly acceptable methodology that provides very high test coverage, but for large circuits, the growing test data volume causes a significant increase in test cost because of much longer test time and elevated tester memory requirements. Test compression or scan compression provides great reduction in test data volume and test time required by adding on-chip decompressor and compactor. In this paper comparative analysis are made for Broadcast, XOR decompressor along with XOR, MISR and Hybrid compactors with respect to test coverage, test cycles required and test data volume by considering Flash Interface as CUT. From the experiments, it is observed that XOR decompressor with MISR compactor architecture provides 17.31% to 49.76% reduction in test data volume compared to other architectures, with 99.76% of fault coverage, 16694 test cycles and 2104µm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of area overhead.

In this paper, we propose a method of test compression for multiple scan designs. Instead of the conventional serial scan chains, the proposed method constructs scan trees in which scan flip-flops are placed and routed in a tree structure. Inputs of the scan trees drive several scan trees of different lengths (height). Since test data volume and test application time are dominated by the scan tree with the maximum height among the constructed scan trees, the proposed method distributes the scan flip-flops to the scan trees so as to minimize the maximum height of the scan trees. In addition, the proposed method modifies the given test vectors to maximize the reduction in test application time. Experimental results for ISCAS-89 benchmark circuits show that the proposed method could reduce, on the average, test data volume by 77% compared with the conventional multiple scan design. The scan tree construction enlarges the number of scan outputs required. However test data volume could be reduced by 66% even if the number of scan outputs is limited.

Recently design for manufacturability (DFM) has been required to achieve higher process yield. Information obtained from silicon by testing and/or fault analysis is sometimes fed back for redesign of VLSI circuits. In this paper we propose a method to maximize defect coverage of a test set initially generated for stuck-at faults in a full scan sequential circuit by using feed back information from fault analysis. If a test set for more complex faults than stuck-at faults is generated, higher defect coverage would be obtained. Such a test set, however, would have a large number of test vectors, and hence the test costs would go up. The proposed method improves defect coverage of the test set by not adding new test vectors but modifying test vectors with the information obtained from fault analysis. Therefore there are no negative impacts on test data volume and test application time. The initial fault coverage for stuck-at faults of the test set is guaranteed with modified test vectors. In this paper we focus on detecting as many as possible non-feedback AND/OR-type bridging faults. Experimental results show that the proposed method significantly decreases the number of non-feedback AND/OR-type bridging faults undetected by a test set generated for stuck-at faults.

This paper presents a new test-data compression technique that uses exactly nine codewords. Our technique aims at precomputed data of intellectual property cores in system-on-chips and does not require any structural information of cores. The technique is flexible in utilizing both fixed- and variable-length blocks. In spite of its simplicity, it provides significant reduction in test-data volume and test-application time. The decompression logic is very small and can be implemented fully independent of the precomputed test-data set. Our technique is flexible and can be efficiently adopted for single- or multiple-scan chain designs. Experimental results for ISCAS'89 benchmarks illustrate the flexibility and efficiency of the proposed technique.

Nowadays System on Chip (SoC) is expected to perform a large number of applications as per the requirement of customers. Increase in the number of applications leads to an increase in the number of cores inside the SoC. Customers want to use a large number of applications in their product but in a cheap price. In this price competitive market, the manufacturer can not increase the price above a certain range in order to sustain in the market. It is decisive to have a high-quality product with the low price. Testing each core thoroughly can require high amount of time and increases the test economics. Hence it is better to cover significant faults only and test the cores partially. In this paper, we propose a method for incomplete testing of the SoC cores, which recedes Test Power (TP) and Test Data Volume (TDV). Our method persists significant fault coverage and tests most of the significant faults. We also propose a power aware Test access mechanism (TAM) architecture compatible with the reduced test vectors. It provides a trade-off between quality of product and testing parameters (i.e., TP, TDV). Results from experiments exhibit an effective reduction in TDV, TP with a nominal compromise on the quality of testing.

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, we propose in this paper to modify an existing test data compression technique (Wang Z, Chakrabarty K in Test data compression for IP embedded cores using selective encoding of scan slices. IEEE International Test Conference, paper 24.3, 2005) so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded Intellectual Property (IP) cores. Compared to the initial solution that fill don't-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS'89 and ITC'99 benchmark circuits and on a number of industrial circuits. Results show that up to 14× reduction in test data volume and 98% test power reduction can be obtained simultaneously.

Integrated circuit (IC) chip designs relying on Random Access Scan (RAS) architecture for post-production structural tests typically provide lower test power dissipation, test data volume, and test application time comparedto the classical serial scan-based Design for Test (DFT) methodology. However, previous RAS schemes incur high signal routing and test area overheads relative to the serial scan way. Unlike serial scan schemes, previous RAS schemes have not been effectively combined with test compression to further reduce test application time and test data volume. Authors have already formally documented a locally addressed (segmented) and compressed Segmented RAS (SRAS) architecture with low area overhead and test application time. This paper describes the SRAS architecture in more detail and provides comparative experimental results. Area overhead is reduced using test access hierarchy (segmented), while adding compression to RAS lowers the test application time.

Three issues that are dominating test research today are test application time, test data volume and test power. Researchers have focused on these issues mostly considering the popular serial scan architecture for its relatively low hardware overhead while ignoring the fact that exponential drop in hardware cost offers opportunities for implementing a test architecture that previously may have been unacceptable. This paper takes such a paradigm shift into account and studies the simultaneous solution of all three problems of serial scan by making use of progressive random access scan test architecture. This architecture only increases the hardware cost marginally while providing marked improvements for the three issues. This paper explains the test architecture and then develops a test generation methodology which reduces the test application time by nearly 75%, test data volume by 50% for the benchmark circuits. Above all, the architecture is inherently so efficient that it reduces the test power by nearly 99% or more of the test power consumption compared to serial scan

Combinational circuits implemented with exclusive-or gates are used for on-chip generation of deterministic test patterns from compressed seeds. Unlike major test compression techniques, this technique doesn't require test pattern generation with don't cares. Experimental results on industrial designs demonstrate that this new XPAND technique achieves exponential reduction in test data volume and test time compared to traditional scan and significantly outperforms existing test compression tools. The XPAND technique is currently being used by several industrial designs.