Fault-Tolerant Traffic-Aware Routing Algorithm for 3-D Photonic Networks-on-Chip

The convergence of three-dimensional (3D) technology and network-on-chip(NoC), the so-called 3D NoC, bring out new architectures and higher performance than traditional 2D NoCs. However, cost is always the dominant factor of adoption of a new technology. In order to evaluate the economic feasibility of volume production of different architectures of 3D NoCs, we compare the fabrication costs of four 3D NoC architectures: 3D mesh, 3D stacked mesh, ciliated mesh and separated mesh, and analyze the variation of costs of different designs with increasing number of processing cores. Conclusion is drawn that when the number of gates is relatively small, 3D mesh and 3D stacked mesh are recommendable, however, when the number of gates is large, 3D mesh and ciliated mesh are cost-efficient than 3D stacked mesh and separated mesh. To the author's knowledge, this is the first disquisition on costs of different architectures of 3D NoCs. It provides economic reference to designing 3D NoCs for volume production in the future.

Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on Chip (NoC) interconnect for a 3D SoC that not only meets the application performance constraints, but also the constraints imposed by the 3D technology, is a significant challenge. In this work we present a design tool, SunFloor 3D, to synthesize application-specific 3D NoCs. The proposed tool determines the best NoC topology for the application, finds paths for the communication flows, assigns the network components on to the 3D layers and performs a placement of them in each layer. We perform experiments on several SoC benchmarks and present a comparative study between 3D and 2D NoC designs. Our studies show large improvements in interconnect power consumption (average of 38%) and delay (average of 13%) for the 3D NoC when compared to the corresponding 2D implementation. Our studies also show that the synthesized topologies result in large power (average of 54%) and delay savings (average of 21%) when compared to standard topologies.

Simulation environment for link energy estimation in networks-on-chip with virtual channels

The density of integration in a single chip has progressed by use of the deep submicron of VLSI design rule. Systems on a chip (for short, SoCs), i.e., several functional cores being integrated in a single chip, have become the mainstream technology. On the other hand, A Network on a Chip (NoC), i.e., a communication-centric platform, offers an on-chip interconnection network. The NoC is one of the on-chip communication systems. The NoC is used in place of conventional shared bus systems. There are many NoC topologies for connecting cores to each other, such as Mesh, Ring, Spider on, and so on. To evaluate the NoC topologies, a simulation based approach was used for the modeling and analysis of the topologies. However, some properties of the topologies could affect the performance of the NoC systems. This paper describes about the performances of the topologies about the communication aspects by the simulation based approach.

Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture

The adoption of a 3D Network-on-Chip (NoC) design depends on the performance and manufacturing cost of the chip. Therefore, a study of Through Silicon Via (TSV), that connects different layers of a 3D chip, is crucial. In this paper, we analysis the impact of TSV design in 3D NoCs. A 3D NoC with five layers is modeled based on modern 2D chips. We discuss the TSV number required for a 3D NoC. Different placements of half and quarter layer-layer connections are explored. We present benchmark results using a cycle accurate full system simulator based on realistic workloads. Experiments show that under different workloads, the average network latencies in full and half layer-layer connection are reduced by 5.24% and 2.18% respectively, compared with quarter design. Our analysis and experiment results provide a guideline for designing TSVs in 3D NoCs to leverage the tradeoff between performance and manufacturing cost.

With complexities of systems-on-chips (SoCs) rising almost daily, the system designers have been searching for new design methodology that can handle given complexities with decreased times-to-market. The obvious solution that comes to mind is increasing the level of abstraction. However the system designers also care about the system architectures, HW/SW performance, and communication protocols. Furthermore, the transaction-level model (TLM) can satisfy the requests on complex design with relative high simulation speed and well performance evaluation. In this paper, we implement a TLM-based network-on-chip (NoC) platform and share-bus system architecture with SystemC. We also implement the H.263 encoder as the system application, and apply a design methodology at electronic-system level (ESL) to make design modeling, design space exploration and performance evaluation. Out platform is able to evaluate performance in relatively short time, obtain important information and complete the design more instinctively. In addition, we compare and contrast the NoC and share-bus system architectures in terms of evaluation performance. In experimental result, the performance bottleneck in communication congestion is solved well by using the NoC instead of using the share-bus design.

Approximate communication for energy-efficient network-on-chip

The continuous improving of semiconductor technology integrates more processors into a single chip. While integrate multiple processors into a chip, the interconnection network of among the cores become a dominant performance bottleneck. Accordingly, this paper provides a new on-chip interconnection network, called Self Similar Cubic (SSC), for many-core architectures. By cooperating with proposed linking mechanism, routing algorithm, and switching architectures, SSC has better scalability, on-chip fabrication possibility, and high communication performance, than conventional on-chip networks, such as Mesh, and Hypercube. In this paper, the comparison of performance and area cost are proposed. The analysis results reveal that SSC can provide higher throughput and lower area cost than other on-chip networks. The performance per area cost of SSC is five times better than that of Mesh.

3D integration, a breakthrough technology to achieve Moore and More Than Moore, provides numerous benefits such as better performance, lower power consumption, and wide bandwidth by vertical interconnects and 3D stacking. These vertical interconnects enable design of high performance 3D Network-on-Chip (NoC) as a communication backbone for massive manycore platforms. However, existing 3D NoCs are still bottlenecked due to simple extension of 2D architectures without fully exploiting the advantages of the 3D integration. Moreover, the anticipated performance gain of 3D NoC-enabled manycore chips will be compromised due to potential failures of through silicon vias (TSVs) that are predominantly used as vertical interconnects. To address these problems, we explore a holistic design methodology starting from the physical layer to the overall interconnection architecture where the vertical data exchange takes place through contactless links using near field inductive coupling (NFIC).

Network-on-chip (NoC) has emerged as a vital factor that determines the performance and power consumption of many-core systems. This paper proposes a hybrid scheme for NoCs, which aims at obtaining low latency and low power consumption. In the presented hybrid scheme, a novel switching mechanism, called virtual circuit switching, is proposed to intermingle with circuit switching and packet switching. Flits traveling in virtual circuit switching can traverse the router with only one stage. In addition, multiple virtual circuit-switched (VCS) connections are allowed to share a common physical channel. Moreover, a path allocation algorithm is proposed in this paper to determine VCS connections and circuit-switched connections on a mesh-connected NoC, such that both communication latency and power are optimized. A set of synthetic and real traffic workloads are exploited to evaluate the effectiveness of the proposed hybrid scheme. The experimental results show that our proposed hybrid scheme can efficiently reduce the communication latency and power. For instance, for real traffic workloads, an average of 20.3% latency reduction and 33.2% power saving can be obtained when compared with the baseline NoC. Moreover, when compared with the NoC with virtual point-to-point connections (VIP), the proposed hybrid scheme can reduce the latency by 6.8% with the power decreasing by 11.3% averagely.

Mapping IP cores to an on-chip network is an important step in Network-on-Chip (NoC) design and affects the performance of NoC systems. A mapping optimisation algorithm and a fault-tolerant mechanism are proposed in this article. The fault-tolerant mechanism and the corresponding routing algorithm can recover NoC communication from switch failures, while preserving high performance. The mapping optimisation algorithm is based on scatter search (SS), which is an intelligent algorithm with a powerful combinatorial search ability. To meet the requests of the NoC mapping application, the standard SS is improved for multiple objective optimisation. This method helps to obtain high-performance mapping layouts. The proposed algorithm was implemented on the Embedded Systems Synthesis Benchmarks Suite (E3S). Experimental results show that this optimisation algorithm achieves low-power consumption, little communication time, balanced link load and high reliability, compared to particle swarm optimisation and genetic algorithm.

Advanced Artificial Intelligence (AI) systems that process vast feature sets can be designed using Deep Neural Networks (DNN). The popularity and prevalence of DNN based tasks are mainly due to their ability to achieve state of the art accuracy. However, DNN based systems are computationally intensive with heavy on-chip and off-chip data movement demands. Efficient hardware accelerators with systematized interconnection platform support handling this insistent computation and fast communication requirements. With rise in accelerator complexity, it is important to identify and solve communication overheads imposed due to heavy data movement in the system. Need for increased data transfers come as a consequence of complex computations and structure of data storage hierarchy in different DNN models. Multi-core system with underlying Network on Chip (NoC) framework is a promising design choice for implementing DNN based systems with diverse layers. Data movement plays a vital role in deciding performance of such systems. Analysing metrics that affect latency and energy/power efficiency of system is thus crucial in deciding performance enhancement of these DNN inference accelerators. This paper quantifies the communication overheads associated with accelerating different DNN models which use NoC as its basic communication platform.

The centralized methods for connection allocation in a circuit-switched network-on-chip (NoC) based on time-division multiplexing (TDM) may pose serious performance and scalability issues in large-scale networks due to the 1) limited path search speed, 2) increasing allocation request rate at central unit and 3) the increasing communication cost between the central unit and NoC nodes. This paper tackles this problem by proposing a combined centralized-distributed approach that splits the original NoC into multiple non-overlapping logical partitions, each of them served by a dedicated NoC-Manager unit. The NoC-Manager employs fast trellis-search shortest path algorithm enabling local path search inside the associated NoC partition, while a set of NoC-Managers jointly combine the partial results in a distributed manner in order to find the most likely global path. This approach attempts to combine the benefits of distributed and centralized systems, whilst the experimental results demonstrate its high potential regarding performance and scalability improvement.

On-chip network design has become an increasingly important component of computer architecture. the cell broadband engine's element interconnect bus, with its four data rings and common command bus for end-to-end transaction control, interconnects more nodes than most commercial on- chip networks. to help understand on-chip network design and performance issues in the context of a commercial multicore chip, this article evaluates the ElB network using conventional latency and throughput characterization methods.