Combined Centralized and Distributed Connection Allocation in Large TDM Circuit Switching NoCs

In this paper we present the HAsim FPGA-accelerated simulator. HAsim is able to model a shared-memory multicore system including detailed core pipelines, cache hierarchy, and on-chip network, using a single FPGA. We describe the scaling techniques that make this possible, including novel uses of time-multiplexing in the core pipeline and on-chip network. We compare our time-multiplexed approach to a direct implementation, and present a case study that motivates why high-detail simulations should continue to play a role in the architectural exploration process.

This article proposes a circuit-switched router that combines Spatial Division Multiplexing (SDM) and Time Division Multiplexing (TDM) in order to increase path diversity in the router while sharing channels among multiple connections. In this way, the probability of establishing paths through the network is increased, thereby significantly reducing contention in the network. Furthermore, Quality of Service (QoS) is easily guaranteed. The proposed router was synthesized on an Stratix III 3SL340F FPGA device. A 4 × 4 2D Mesh SDM-TDM Network-on-Chip (NoC) was built with the proposed router and synthesized on the 3SL340F FPGA device. The 4 × 4 2D Mesh SDM-TDM NoC was used to build on an FPGA device, a Multiprocessor System-on-Chip (MPSoC) platform consisted of 16 Nios II/f processors, 16 20-KB On-chip Memories, and 16 Network Interfaces. Synthesis results of the MPSoC platform show that the proposed router architecture can be used to built large practicable MPSoC platforms with the proposed NoC architecture with a reasonable hardware overhead and appreciable clock frequency. Simulation results show that combining SDM and TDM techniques in a router allows the highest probability of establishing paths through the network.

On-chip network design has become an increasingly important component of computer architecture. the cell broadband engine's element interconnect bus, with its four data rings and common command bus for end-to-end transaction control, interconnects more nodes than most commercial on- chip networks. to help understand on-chip network design and performance issues in the context of a commercial multicore chip, this article evaluates the ElB network using conventional latency and throughput characterization methods.

This paper explores the design of a circuit-switched network-on-chip (NoC) based on time-division-multiplexing (TDM) for use in hard real-time systems. Previous work has primarily considered application-specific systems. The work presented here targets general-purpose hardware platforms. We consider a system with IP-cores, where the TDM-NoC must provide directed virtual circuits -- all with the same bandwidth -- between all nodes. This may not be a frequent scenario, but a general platform should provide this capability, and it is an interesting point in the design space to study. The paper presents an FPGA-friendly hardware design, which is simple, fast, and consumes minimal resources. Furthermore, an algorithm to find minimum-period schedules for all-to-all virtual circuits on top of typical physical NoC topologies like 2D-mesh, torus, bidirectional torus, tree, and fat-tree is presented. The static schedule makes the NoC time-predictable and enables worst-case execution time analysis of communicating real-time tasks.

Service Level Agreements (SLA) are employed to ensure the performance of Cloud solutions. When a component fails, the importance of logs increases significantly. All departments may turn to logs to determine the cause of the issue and find the party at fault. The party at fault may be motivated to tamper with the logs to hide their role. We argue that the critical nature of Cloud logs calls for immutability and verification mechanism without the presence of a single trusted party. This article proposes such a mechanism by describing a blockchain-based log storage system, called Logchain, which can be integrated with existing private and public blockchain solutions. Logchain uses the immutability feature of blockchain to provide a tamper-resistance platform for log storage. Additionally, we propose a hierarchical structure to address blockchains’ scalability issues. To validate the mechanism, we integrate Logchain into Ethereum and IBM Blockchain. We show that the solution is scalable and perform the analysis of the cost of ownership to help a reader select an implementation that would address their needs. The Logchain's scalability improvement on a blockchain is achieved without any alteration of blockchains’ fundamental architecture. As shown in this work, it can function on private and public blockchains and, therefore, can be a suitable alternative for organizations that need a secure, immutable log storage platform.

Decoupling Control-Plane from Data-Plane, Software Defined Network (SDN) takes a firm step towards facilitation of management, especially in mission-critical networks, such as data centers and back-bones. To maintain scalability, which is a vital aspect of such networks, many techniques based on the capabilities of hardware and network communications are introduced. However, to cope with scalability issues, less attention is paid to the integrated knowledge gained about underlying network in Control-Plane. To reduce the computing overhead on SDN's controller, a scheme based on extracting similarities among requested flows is presented in this research. Performance evaluation by simulating the proposed method shows significant improvement in scalability of the Controller, while inconsiderable workload is imposed.

As the number of cores on a single chip increased, the inter-core communication system quickly became the performance bottleneck. In order to solve the performance and scalability issues of bus-based systems, Network-on-chip (NoC) was proposed. This eventually met its own bottleneck and several technologies sprouted out from NoC research. The most commonly researched upgrade to NoCs was 3D NoCs, which utilized stacked routers to reduce the maximum hop count. Other researchers have looked at alternative transmission mediums, such as photonics. These technologies can be combined to give great performance and power benefits but can be slowed down by congestion in their path-setup phase. In order to solve this issue, we propose a traffic-aware routing algorithm that can evenly distribute the traffic throughout the chip, all while simultaneously avoiding faulty nodes. The results show that the proposed algorithm was successful in balancing the load across the chip and that the performance costs of the algorithm were mostly offset by the benefits of reducing blocked paths.

This research proposes a novel approach to global path and resource planning for lunar rovers. The proposed method incorporates a range of constraints, including static, time-variant, and path-dependent factors related to environmental conditions and the rover’s internal resource status. These constraints are integrated into a grid map as a penalty function, and a reinforcement learning-based framework is employed to address the resource constrained shortest path problem (RCSP). Compared to existing approaches referenced in the literature, our proposed method enables the simultaneous consideration of a broader spectrum of constraints. This enhanced flexibility leads to improved path search optimality. To evaluate the performance of our approach, this research applied the proposed learning architecture to lunar rover path search problems, generated based on real lunar digital elevation data. The simulation results demonstrate that our architecture successfully identifies a rover path while consistently adhering to user-defined environmental and rover resource safety criteria across all positions and time epochs. Furthermore, the simulation results indicate that our approach surpasses conventional methods that solely rely on environmental constraints.

Network densification is essential to enhance the areal capacity of future wireless networks, for which the user-centric network is a promising solution. In the perspective of network scalability, user association and cooperative beamforming (BF) among the base stations (BSs) should be designed elaborately to manage strong interference from nearby BSs. However, practical systems with hardware impairments including nonlinearity of power amplifiers may disturb these techniques and make the network difficult to be scalable. The nonlinearity of power amplifiers affects not only radio frequency (RF)-level signal but also performance according to the number of user equipments (UEs), resulting in necessity of re-designing network-level operations including BS-UE association. This paper proposes a deep learning-based cooperative BF framework for distributed networks with nonlinear power amplifiers. To optimize the cooperative BF for complicated nonlinear systems, we adopt unsupervised learning approach with constraints. To reduce the communication overhead of the network, we propose a novel neural network structure, from which the BSs can perform the cooperative BF in distributed manner. In particular, the information exchange between the central unit and the local BSs is reduced by designing neural network so that the local channel state information are utilized only in the local BSs while the central unit utilizes only covariance matrices. We show that the proposed scheme achieves a higher effective sum rate compared to the baseline schemes by adjusting the user association, BF, and power allocation to control interference and nonlinear distortion with reduced communication overhead.

The increasing trend in the number of cores on a single chip has led to scalability and bandwidth issues in bus-based communication. Network-on-chip (NoC) techniques have emerged as a solution that provides a much needed flexibility and scalability in the era of multi-cores. This article presents an optimal integer linear programming (ILP) formulation and a simulated annealing (SA) solution to thermal and power-aware test scheduling of cores in an NoC-based SoC using multiple clock rates. The methods have been implemented and results on various benchmarks are presented.

Scalability studies and computations using the largest grids to date for free-surface flows are performed using message-passing interface (MPI)-based CFDShip-Iowa toolbox curvilinear (V4) and Cartesian (V6) grid solvers on Navy high-performance computing systems. Both solvers show good strong scalability up to 2048 processors, with V6 showing somewhat better performance than V4. V6 also outperforms V4 in terms of the memory requirements and central processing unit (CPU) time per time-step per grid point. The explicit solvers show better scalability than the implicit solvers, but the latter allows larger time-step sizes, resulting in a lower total CPU time. The multi-grid HYPRE solver shows better scalability than the portable, extensible toolkit for scientific computation solver. The main scalability bottleneck is identified to be the pressure Poisson solver. The memory bandwidth test suggests that further scalability improvements could be obtained by using hybrid MPI/open multi-processing (OpenMP) parallelization. V4-detached eddy simulation (DES) on a 300 M grid for the surface combatant model DTMB 5415 in the straight-ahead condition provides a plausible description of the vortical structures and mean flow patterns observed in the experiments. However, the vortex strengths are over predicted and the turbulence is not resolved. V4-DESs on up to 250 M grids for DTMB 5415 at 20° static drift angle significantly improve the forces and moment predictions compared to the coarse grid unsteady Reynolds averaged Navier–Stokes, due to the improved resolved turbulence predictions. The simulations provide detailed resolution of the free-surface and breaking pattern and vortical and turbulent structures, which will guide planned experiments. V6 simulations on up to 276 M grids for DTMB 5415 in the straight-ahead condition predict diffused vortical structures due to poor wall-layer predictions. This could be due to the limitations of the wall-function implementation for the immersed boundary method.

Ant Colony Optimization (ACO) is a problem-solving technique inspired by the behavior of real-world ant colony. ACO-based routing also has high potential on balancing the traffic load in the domain of Network-on-Chip (NoC), where the performance is generally dominated by traffic distribution and routing. Since the pheromone in ACO provides both spatial and temporal network information, we find ACO-based routing suitable for reducing the probability of deadlock and its penalty. With the three schemes inspired by the behavior of ants and named as ACO-based Deadlock-Aware Routing (ACO-DAR), our simulation shows that the occurrence of deadlock can be greatly suppressed and the network performance also improves as a consequence. Moreover, ACO-DAR makes use of the existing hardware of the original ACO-based routing, so the area overhead is minor and ACO-DAR is thus cost-effective.

Multi-core systems-on-chip are becoming state-of-the-art. Therefore, there is a need for a fast and energy-efficient interconnect to take full advantage of the computational capabilities. Integration of silicon photonics with a traditional electrical interconnect in a Network-on-Chip (NoC) proposes a promising solution for overcoming the scalability issues of electrical interconnect. In this article, we derive and evaluate prediction modeling techniques for the design space exploration (DSE) of application-specific communication architectures for an Optical Network-on-Chip (ONoC). Our proposed model accurately predicts network packet latency, contention delay, and the static and dynamic energy consumption of the network. This work specifically addresses the challenge of accurately estimating performance metrics of the entire design space without having to perform time-consuming and computationally intensive exhaustive simulations. The proposed technique, based on machine learning (ML), can build accurate prediction models using only 10% to 50% (best case and worst case) of the entire design space. The accuracy, expressed as R 2 (Coefficient of Determination) is 0.99901, 0.99967, 0.99996, and 0.99999 for network packet latency, contention delay, static energy consumption, and dynamic energy consumption, respectively, in six different benchmarks from the Splash-2 benchmark suite, chosen among 6 different machine learning prediction models.

This review examines the increasing application of artificial intelligence (AI) and/or machine learning (ML) in microalgae processes, focusing on their ability to improve production efficiency, yield, and process control. AI/ML technologies are used in various aspects of microalgae processes, such as real-time monitoring, species identification, the optimization of growth conditions, harvesting, and the purification of bioproducts. Commonly employed ML algorithms, including the support vector machine (SVM), genetic algorithm (GA), decision tree (DT), random forest (RF), artificial neural network (ANN), and deep learning (DL), each have unique strengths but also present challenges, such as computational demands, overfitting, and transparency. Despite these hurdles, AI/ML technologies have shown significant improvements in system performance, scalability, and resource efficiency, as well as in cutting costs, minimizing downtime, and reducing environmental impact. However, broader implementations face obstacles, including data availability, model complexity, scalability issues, cybersecurity threats, and regulatory challenges. To address these issues, solutions, such as the use of simulation-based data, modular system designs, and adaptive learning models, have been proposed. This review contributes to the literature by offering a thorough analysis of the practical applications, obstacles, and benefits of AI/ML in microalgae processes, offering critical insights into this fast-evolving field.

PHASE SPACE NAVIGATOR: TOWARDS AUTOMATING CONTROL SYNTHESIS IN PHASE SPACES FOR NONLINEAR CONTROL SYSTEMS